參數(shù)資料
型號: AD9148-M5372-EBZ
廠商: Analog Devices Inc
文件頁數(shù): 18/72頁
文件大小: 0K
描述: BOARD EVAL FOR AD9149, ADL5372
設(shè)計資源: AD9148-M5372-EBZ Schematic
AD9148-M5372-EBZ BOM
AD9148-M5372-EBZ Gerber Files
標(biāo)準(zhǔn)包裝: 1
系列: *
Data Sheet
AD9148
Rev. B | Page 25 of 72
Addr
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
0x1F
Chip ID
Chip ID[7:0]
0x07
0x201
Coeff I Byte 0
0
Coeff_1i[3:0]
Coeff_0i[2:0]
0x00
0x211
Coeff I Byte 1
Coeff_3i[2:0]
Coeff_2i[4:0]
0xC0
0x221
Coeff I Byte 2
Coeff_4i[2:0]
0
Coeff_3i[6:3]
0xEF
0x231
Coeff I Byte 3
0
Coeff_4i[9:3]
0x7F
0x241
Coeff Q Byte 0
0
Coeff_1q[3:0]
Coeff_0q[2:0]
0x69
0x251
Coeff Q Byte 1
Coeff_3q[2:0]
Coeff_2q[4:0]
0xE6
0x261
Coeff Q Byte 2
Coeff_4q[2:0]
0
Coeff_3q[6:3]
0x0D
0x271
Coeff Q Byte 3
0
Coeff_4q[9:3]
0x00
0x281
I phase adj LSB
Phase Word I[7:0]
0x00
0x291
I phase adj
MSB
Phase Word I[9:8]
0x00
0x2A1
Q phase adj
LSB
Phase Word Q[7:0]
0x00
0x2B1
Q phase adj
MSB
Phase Word Q[9:8]
0x00
0x2C1
I DC offset LSB
DC Offset I[7:0]
0x00
0x2D1
I DC offset
MSB
DC Offset I[15:8]
0x00
0x2E1
Q DC offset
LSB
DC Offset Q[7:0]
0x00
0x2F1
Q DC offset
MSB
DC Offset Q[15:8]
0x00
0x301
IDAC FSC adj
IDAC FSC Adj[7:0]
0xF9
0x311
IDAC control
IDAC sleep
IDAC FSC Adj[9:8]
0x01
0x321
AUX IDAC data
AUX IDAC Data[7:0]
0x00
0x331
AUX IDAC
control
AUX IDAC
sign
AUX IDAC
current
direction
AUX IDAC
power-
down
AUX IDAC Data[9:8]
0x00
0x341
QDAC FSC adj
QDAC FSC Adj[7:0]
0xF9
0x351
QDAC control
QDAC sleep
QDAC FSC Adj[9:8]
0x01
0x361
AUX QDAC
data
AUX QDAC Data[7:0]
0x00
0x371
AUX QDAC
control
AUX QDAC
sign
AUX QDAC
current
direction
AUX QDAC
power-
down
AUX QDAC Data[9:8]
0x00
0x381
SED_S0_L
SED Compare Pattern Sample0[7:0]
0xB6
0x391
SED_S0_H
SED Compare Pattern Sample0[15:8]
0x7A
0x3A1
SED_S1_L
SED Compare Pattern Sample1[7:0]
0x45
0x3B1
SED_S1_H
SED Compare Pattern Sample1[15:8]
0xEA
0x3C1
SED3_S2_L
SED Compare Pattern Sample2[7:0]
0x16
0x3D1
SED3_S2_H
SED Compare Pattern Sample2[15:8]
0x1A
0x3E1
SED4_S3_L
SED Compare Pattern Sample3[7:0]
0xC6
0x3F1
SED4_S3_H
SED Compare Pattern Sample3[15:8]
0xAA
0x40
SED control/
status
SED
compare
enable
Port B
error
detected
Port A
error
detected
Auto-
clear
enable
Port B
compare
failed
Port A
compare
failed
Compare
passed
0x00
0x411
SED_R_L
SED Status Rising Edge Samples[7:0]
0x421
SED_R_H
SED Status Rising Edge Samples[15:8]
0x431
SED_F_L
SED Status Falling Edge Samples[7:0]
0x441
SED_F_H
SED Status Falling Edge Samples[15:8]
0x501
I gain control
I Gain[7:0]
0x40
0x511
Q gain control
Q Gain[7:0]
0x40
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