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| 型號： | AD9148-M5372-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 64/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9149, ADL5372 |
| 設(shè)計資源： | AD9148-M5372-EBZ Schematic AD9148-M5372-EBZ BOM AD9148-M5372-EBZ Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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Data Sheet
AD9148
Rev. B | Page 67 of 72
INTERFACE TIMING VALIDATION
The AD9148 provides on-chip sample error detection (SED)
circuitry that simplifies verification of the input data interface.
The SED compares the input data samples captured at the digital
input pins with a set of comparison values. The comparison values
are loaded into registers through the SPI port. Differences between
the captured values and the comparison values are detected and
stored. Options are available for customizing SED test sequencing
and error handling.
SED OPERATION
The SED circuitry operates on two data sets, one for each data
port, each made up of four 16-bit input words, denoted as S0,
S1, S2, and S3. To properly align the input samples, the first
data-word (that is, S0) is indicated by asserting FRAME for at
least one complete input sample.
Figure 92 shows the input timing of the interface for each port.
The FRAME signal can be issued once at the start of the data
transmission, or it can be asserted repeatedly at intervals coinciding
with the S0 and S1 data-words.
FRAMEA/
FRAMEB
A[15:0]/
B[15:0]
S3
S1
S0
S2
S0
S1
08910-
089
Figure 92. Timing Diagram of Extended FRAME Signal Required to Align
Input Data for SED
The SED has five flag bits (Register 0x40, Bit 0, Bit 1, Bit 2, Bit 5
and Bit 6) that indicate the results of the input sample comparisons.
The sample error detected bit (Bit 5, Register 0x40 for Port A
and Bit 6, Register 0x40 for Port B) is set when an error is detected
and remains set until cleared. The SED also provides registers
that indicate which input data bits experienced errors (Register 0x41
through Register 0x44). These bits are latched and indicate the
accumulated errors detected until cleared.
The autoclear mode has two effects: it activates the compare fail
bits and the compare pass bit (Register 0x40, Bit 2, Bit 1, and Bit 0)
and changes the behavior of Register 0x41 through Register 0x44.
The compare pass bit sets if the last comparison indicated that
the sample was error free. The compare fail bit sets if an error
is detected. The compare fail bit is cleared automatically by the
reception of eight consecutive error-free comparisons. When
autoclear mode is enabled (Bit 3, Register 0x40), Register 0x41
through Register 0x44 accumulate errors as previously described
but reset to all 0s after eight consecutive error-free sample
comparisons are made.
The sample error, compare pass, and compare fail flags can be
configured to trigger an IRQ when active, if desired. This is
done by enabling the appropriate bits in the event flag register
(Register 0x07).
SED EXAMPLE
Normal Operation
The following example illustrates the SED configuration for
continuously monitoring the input data and assertion of an IRQ
when a single error is detected.
1. Write to the following registers to enable the SED and load
the comparison values:
Register 0x40 → 0x80
Register 0x00[4] → 0 (to configure Port A SED)
Register 0x38 → S0[7:0]
Register 0x39 → S0[15:8]
Register 0x3A → S1[7:0]
Register 0x3B → S1[15:8]
Register 0x3C → S2[7:0]
Register 0x3D → S2[15:8]
Register 0x3E → S3[7:0]
Register 0x3F → S3[15:8]
Register 0x00[4] → 1 (to configure Port B SED)
Register 0x38 → S0[7:0]
Register 0x39 → S0[15:8]
Register 0x3A → S1[7:0]
Register 0x3B → S1[15:8]
Register 0x3C → S2[7:0]
Register 0x3D → S2[15:8]
Register 0x3E → S3[7:0]
Register 0x3F → S3[15:8]
Comparison values can be chosen arbitrarily; however,
choosing values that require frequent bit toggling provides
the most robust test.
2. Enable the SED error detect flag to assert the IRQ pin.
Register 0x05 → 0x04
3. Begin transmitting the input data pattern.
If IRQ is asserted, read Register 0x40 and Register 0x41 through
Register 0x44 with Bit 4, Register 0x00 = 0 for Port A and with
Bit 4, Register 0x00 = 1 for Port B, to verify that a SED error was
detected, and determine which input bits were in error. The bits in
Register 0x41 through Register 0x44 are latched; therefore, the bits
indicate any errors that occurred on those bits throughout the test
and not just the errors that caused the error detected flag to be set.
Note that the FRAME signal is not required during normal
operation when the device is configured for dual-port mode.
To enable the alignment of the S0 sample as previously described
requires the use of both the FRAMEA and FRAMEB signals.
The timing diagrams for single-port and byte modes are the same as
during normal operation and are shown in Figure 47 and Figure 48,
respectively. For single-port and byte mode, only FRAMEA and
the IRQs for Port A should be used. The FRAMEA rising edge
should always be aligned with the first sample of the data trans-
mission. There should not be another rising edge until four complete
words of data are received. This means four data samples for dual-
port mode and eight data samples for single-port and byte modes.
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