參數(shù)資料
型號(hào)： AD9148-M5372-EBZ
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 57/72頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9149, ADL5372
設(shè)計(jì)資源： AD9148-M5372-EBZ Schematic
AD9148-M5372-EBZ BOM
AD9148-M5372-EBZ Gerber Files
標(biāo)準(zhǔn)包裝： 1
系列： *
AD9148
Data Sheet
Rev. B | Page 60 of 72
Transmit DAC Output Configurations
The optimum noise and distortion performance of the AD9148
is realized when it is configured for differential operation. The
common-mode error sources of the DAC outputs are reduced
significantly by the common-mode rejection of a transformer or
differential amplifier. These common-mode error sources include
even-order distortion products and noise. The enhancement in
distortion performance becomes more significant as the frequency
content of the reconstructed waveform increases and/or its
amplitude increases. This is due to the first-order cancellation
of various dynamic common-mode distortion mechanisms,
digital feedthrough, and noise.
IOUT1_P/IOUT3_P
IOUT1_N/IOUT3_N
IOUT2_N/IOUT4_N
IOUT2_P/IOUT4_P
RO
VIP +
VIN –
VOUTI
RO
VQP +
VQN –
VOUTQ
0
89
10
-0
76
Figure 78. Basic Transmit DAC Output Circuit
Figure 78 shows the most basic DAC output circuitry. A pair
of resistors, RO, are used to convert each of the complementary
output currents to a differential voltage output, VOUT. Because
the current outputs of the DAC are high impedance, the differential
driving point impedance of the DAC outputs, ROUT, is equal to
2 × RO. Figure 79 illustrates the output voltage waveforms.
VPEAK
VP
TIME
VN
VOM
VP
08
91
0-
077
Figure 79. Voltage Output Waveforms
The common-mode signal voltage, VCM, is calculated by
O
FS
CM
R
I
V
2
The peak output voltage, VPEAK, is calculated by
VPEAK = IFS × RO
With this circuit configuration, the single-ended peak voltage is
the same as the peak differential output voltage.
Transmit DAC Linear Output Signal Swing
The DAC outputs have a linear output compliance voltage range
of ±1 V that must be adhered to achieve optimum performance.
The linear output signal swing is dependent on the full-scale output
current, IOUTFS, and the common-mode level of the output.
AUXILIARY DAC OPERATION
The AD9148 has four 10-bit auxiliary DACs (AUX1, AUX2, AUX3,
and AUX4). The full-scale output current on these DACs is derived
from the 1.2 V band gap reference and external resistor. The gain
scale from the reference amplifier current, IREF, to the auxiliary
DAC reference current is 16.67 with the auxiliary DAC gain set
to full-scale. This gives a full-scale current of approximately 2 mA
for each auxiliary DAC.
The magnitude of the AUX1 DAC current is controlled via
Bits[1:0], Register 0x33 (MSBs) and Bits[7:0], Register 0x32 (LSBs)
when DAC SPI select = 0 (Bit 4, Register 0x00). The magnitude
of the AUX2 DAC current is controlled via Bits[1:0], Register 0x37
(MSBs) and Bits[7:0], Register 0x36 (LSBs) when DAC SPI select = 0
(Bit 4, Register 0x00). Likewise, the magnitudes of AUX3 DAC
current and AUX4 DAC current are controlled via Register 0x33 to
Register 0x32 and Register 0x37 to Register 0x36, respectively
when DAC SPI Select = 1 (Register 0x00, Bit[4]).
The auxiliary DAC structure is shown in Figure 80. There are
two output signals on each auxiliary DAC. One signal is P, and
the other is N. The auxiliary DAC outputs are not differential.
Only one side of the auxiliary DAC (P or N) is active at one
time. The inactive side goes into a high impedance state (100 kΩ).
Control of the P side and N side for the auxiliary DACs is via
Bit 7, Register 0x33 and Bit 7, Register 0x37 (DAC SPI select is 0
to control AUX1 and AUX2, and DAC SPI select is 1 to control
AUX3 and AUX4).
AUX_P
AUX_N
VB
AUXDAC
DIRECTION
(SOURCE/SINK)
AUXDAC[9:0]
0mA TO 2mA
(SOURCE)
0mA TO 2mA
(SINK)
AUXDAC
SIGN
(P/N)
08
91
0-
078
Figure 80. Auxiliary DAC Structure
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