參數(shù)資料
型號： AD9523BCPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 23/60頁
文件大小： 0K
描述： IC INTEGER-N CLCK GEN 72LFCSP
標(biāo)準包裝： 400
類型： 時鐘/頻率發(fā)生器，扇出緩沖器（分配）
PLL： 是
主要目的： 以太網(wǎng)，光纖通道，SONET/SDH
輸入： CMOS
輸出： HSTL，LVCMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:14
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1GHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 72-LFCSP-VQ（10x10）
包裝： 帶卷 (TR)
配用： AD9523/PCBZ-ND - BOARD EVAL FOR AD9523
Data Sheet
AD9523
Rev. C | Page 3 of 60
REVISION HISTORY
2/13—Rev. B to Rev. C
Deleted VDD1.8_PLL2................................................. Throughout
Changes to Data Sheet Title.............................................................1
Added TJ of 115°C, Table 1 ..............................................................4
Changed VDD3_PLL1, Supply Voltage for PLL1 Typical
Parameter from 22 mA to 37 mA and Changed VDD3_PLL1,
Supply Voltage for PLL1 Maximum Parameter from 25.2 mA to
43 mA, Table 2 ...................................................................................4
Changes to Table 3 ............................................................................5
Added PLL1 Characteristics Section and Table 7; Renumbered
Sequentially........................................................................................6
Changes to Table 9 Summary Statement........................................7
Changes to Pin 7 Description, Table 19 .......................................13
Changed Pin 69 from VDD1.8_PLL2 to NC, Table 19 ..............15
Changes to Figure 23 ......................................................................21
Changes to Clock Distribution Synchronization Section..........25
Changes to Figure 29 ......................................................................26
Added Reset Modes Section and Lock Detect Section ..............26
Added Power-Down Mode Section ..............................................27
Changes to Pin Descriptions Section and Read Section............31
Added Figure 38; Renumbered Sequentially...............................33
Changes to Register Section Definition Group Section ............36
Changes to Power Dissipation and Thermal Considerations
Section ..............................................................................................38
Changes to Table 31 ........................................................................40
Changes to Bits[1:0] Description, Table 40 and Bit 2
Description, Table 41 ......................................................................46
Changes to Bits[7:6] Description, Table 42..................................47
Changes to Bits[1:0] Description, Table 43..................................48
Changes to Bit 4, Bits [3:2] Descriptions, Table 47.....................49
Changed Bit 6 Name from Status PLL2 Feedback Clock to Status
PLL1 Feedback Clock, Table 54.......................................................52
3/11—Rev. A to Rev. B
Added Table Summary, Table 8.......................................................7
Changes to EEPROM Operations Section and Writing to the
EEPROM Section............................................................................34
Changes to 0x01A, Bits[4:3], Table 30..........................................39
Changes to Bits[4:3], Table 40 .......................................................46
Changes to Table 47, Bit 1..............................................................48
11/10—Rev. 0 to Rev. A
Change to General Description.......................................................1
Changes to Table Summary, Table 1...............................................3
Change to Input High Voltage and Input Low Voltage
Parameters and Added Input Threshold Voltage Parameter,
Table 4.................................................................................................4
Change to Junction Temperature Rating, Table 16; Changes
to Thermal Resistance Section ......................................................11
Changes to Table 18 ........................................................................12
Added Figure 14, Renumbered Sequentially...............................16
Edits to Figure 15, Figure 17, and Figure 19................................17
Changes to VCO Calibration Section...........................................22
Changed Output Mode Heading to Multimode Output
Drivers; Changes to Multimode Output Drivers Section;
Added Figure 26..............................................................................23
Added Power Dissipation and Thermal Considerations
Section; Added Table 29, Renumbered Sequentially..................35
Changes to Table 34, Table 35, Table 36, and Table 38...............43
Changes to Address 0x192, Table 50 ............................................48
Changes to Table 52 ........................................................................49
Changes to Table 54 ........................................................................50
7/10—Revision 0: Initial Version
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