參數(shù)資料
型號(hào)： AD9641-80KITZ
廠商： Analog Devices Inc
文件頁數(shù)： 21/36頁
文件大小： 0K
描述： BOARD EVAL FOR AD9641
設(shè)計(jì)資源： AD9641 Gerber Files
AD9641 80KITZ BOM
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 14
采樣率（每秒）： 80M
數(shù)據(jù)接口： 串行，SPI?
輸入范圍： 1.4 ~ 2.1 Vpp
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD9641
已供物品： 板
AD9641
Data Sheet
Rev. B | Page 28 of 36
HARDWARE INTERFACE
The pins described in Table 15 comprise the physical interface
between the user programming device and the serial port of
the AD9641. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note, Micro-
controller-Based Serial Port Interface (SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used
for other devices, it may be necessary to provide buffers between
this bus and the AD9641 to prevent these signals from transi-
tioning at the converter inputs during critical sampling periods.
SPI ACCESSIBLE FEATURES
Table 16 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the AN-877 Application Note, Interfacing to High Speed ADCs
via SPI. The AD9641 part-specific features are described in detail in
Table 16. Features Accessible Using the SPI
Feature Name
Description
Mode
Allows the user to set either power-down mode
or standby mode
Clock
Allows the user to access the DCS, set the
clock divider, set the clock divider phase, and
enable the sync
Offset
Allows the user to digitally adjust the
converter offset
Test I/O
Allows the user to set test modes to have
known data on output bits
Full Scale
Allows the user to set the input full-scale
voltage
JESD204A
Allows user to configure the JESD204A output
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