參數(shù)資料
型號(hào): AD9641-80KITZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 25/36頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD9641
設(shè)計(jì)資源: AD9641 Gerber Files
AD9641 80KITZ BOM
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 1
位數(shù): 14
采樣率(每秒): 80M
數(shù)據(jù)接口: 串行,SPI?
輸入范圍: 1.4 ~ 2.1 Vpp
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD9641
已供物品:
Data Sheet
AD9641
Rev. B | Page 31 of 36
Addr
(Hex)
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default
Notes/
Comments
0x1E
User Test
Pattern 3 MSB
User Test Pattern 3, Bits[15:8]
0x00
0x1F
User Test
Pattern 4 LSB
User Test Pattern 4, Bits[7:0]
0x00
0x20
User Test
Pattern 4 MSB
User Test Pattern 4, Bits[15:8]
0x00
0x21
PLL control
Open
PLL low
encode
rate enable
Open
0x00
Bit 3 must
be enabled
if the ADC
clock rate is
<60 MHz.
0x24
BIST
signature LSB
BIST signature, Bits[7:0]
0x00
Read only.
0x25
BIST
signature
MSB
BIST signature, Bits[15:8]
0x00
Read only.
0x3A
Sync control
Open
Clock
divider
next sync
only
Clock
divider
sync
enable
Master sync
buffer
enable
0x00
JESD204A Configuration Registers
0x60
JESD204A
Link Control
Register 1
Open
Serial tail
bit enable
Serial test
sample
enable
Serial lane
synchroni-
zation
enable
Serial lane alignment
sequence mode
00 = disabled
01 = enabled
10 = reserved
11 = always on
test mode
Frame
alignment
character
insertion
disable
Serial
transmit link
power- down
0x00
0x61
JESD204A
Link Control
Register 2
Local DSYNC mode
00 = individual mode
01 = global mode
10 = DSYNC active mode
11 = DSYNC pin disabled
DSYNC
pin input
inverted
CMOS
DSYNC
input
0 = LVDS
1 = CMOS
Open
Bypass
8b/10b
encoding
Invert
transmit
bits
Mirror serial
output bits
0x00
0x62
JESD204A
Link Control
Register 3
Disable
CHKSUM
Open
Link test generation
input selection
00 = 16-bit data injected
at sample input to the
link
01 = 10-bit data injected
at output of 8b/10b
encoder
10 = reserved
11 = reserved
Open
Link test generation mode
000 = normal operation
001 = alternating checkerboard
010 = 1/0 word toggle
011 = PN sequence, long
100 = PN sequence, short
101 = user test pattern data continuous
110 = user test pattern data single
111 = ramp output
0x00
0x63
JESD204A
Link Control
Register 4
Initial lane assignment sequence repeat count
0x00
0x64
JESD204A
device
identification
number
(DID)
JESD204A serial device identification (DID) number
0x00
0x65
JESD204A
bank
identification
number
(BID)
Open
JESD204A serial bank identification (BID) number
0x00
0x66
JESD204A
lane
identification
number
(LID)
Open
JESD204A serial lane identification (LID) number
0x00
0x6E
JESD204A
scrambler
(SCR) and
lane (L)
configuration
Enable
serial
scrambler
mode (SCR)
Open
Serial lane
control
0 = one lane
per link
(L = 1)
1 = reserved
0x80
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