參數(shù)資料
型號(hào): AD9641-80KITZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 33/36頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD9641
設(shè)計(jì)資源: AD9641 Gerber Files
AD9641 80KITZ BOM
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 1
位數(shù): 14
采樣率(每秒): 80M
數(shù)據(jù)接口: 串行,SPI?
輸入范圍: 1.4 ~ 2.1 Vpp
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD9641
已供物品:
AD9641
Data Sheet
Rev. B | Page 6 of 36
Parameter
Temperature
Min
Typ
Max
Unit
LOGIC INPUT/OUTPUT (SDIO)1
Logic Compliance
CMOS
High Level Input Voltage
Full
1.22
2.1
V
Low Level Input Voltage
Full
0
0.6
V
High Level Input Current
Full
10
+10
μA
Low Level Input Current
Full
38
128
μA
Input Resistance
Full
26
Input Capacitance
Full
5
pF
DIGITAL OUTPUTS
Logic Compliance
Full
CML
Differential Output Voltage (VOD)
Full
0.6
0.8
1.1
V
Output Offset Voltage (VOS)
Full
0.75
DRVDD/2
1.05
V
1 Pull up.
2 Pull down.
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = 1.0 dBFS differential input, and DCS enabled,
unless otherwise noted.
Table 4.
AD9641-80
AD9641-155
Parameter
Temperature
Min
Typ
Max
Min
Typ
Max
Unit
CLOCK INPUT PARAMETERS
Input Clock Rate
Full
640
MHz
Conversion Rate1
Full
40
80
40
155
MSPS
CLK Period—Divide-by-1 Mode (tCLK)
Full
12.5
6.45
ns
CLK Pulse Width High (tCH)
Divide-by-1 Mode, DCS Enabled
Full
3.75
6.25
8.75
1.935
3.225
4.515
ns
Divide-by-1 Mode, DCS Disabled
Full
5.95
6.25
6.55
3.065
3.225
3.385
ns
Divide-by-2 Mode Through Divide-by-8 Mode
Full
0.8
ns
Aperture Delay (tA)
Full
0.78
ns
Aperture Uncertainty (Jitter, tJ)
Full
0.125
ps rms
DATA OUTPUT PARAMETERS
Data Output Period or UI (Unit Interval)
Full
1/(20 × fCLK)
sec
Data Output Duty Cycle
25°C
50
%
Data Valid Time
25°C
0.8
0.75
UI
PLL Lock Time (tLOCK)
25°C
4
μs
Wake Up Time (Standby)
25°C
5
μs
Wake Up Time (Power-Down)2
25°C
2.5
ms
Pipeline Delay (Latency)
Full
23
24
23
24
CLK cycles
Data Rate (NRZ)
25°C
1.6
3.1
Gbps
Deterministic Jitter
25°C
40
ps
Random Jitter at 1.6 Gbps
25°C
9.5
ps rms
Random Jitter at 3.1 Gbps
25°C
5.2
ps rms
Output Rise/Fall Time
25°C
50
ps
TERMINATION CHARACTERISTICS
Differential Termination Resistance
25°C
100
Ω
OUT-OF-RANGE RECOVERY TIME
25°C
2
CLK cycles
1 Conversion rate is the clock rate after the divider.
2 Wake-up time is defined as the time required to return to normal operation from power-down mode.
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