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參數(shù)資料
| 型號： | AD9641-80KITZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 29/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9641 |
| 設(shè)計資源： | AD9641 Gerber Files AD9641 80KITZ BOM |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 80M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 輸入范圍： | 1.4 ~ 2.1 Vpp |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD9641 |
| 已供物品： | 板 |
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Data Sheet
AD9641
Rev. B | Page 35 of 36
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting design and layout of the AD9641 as a system,
it is recommended that the designer become familiar with these
guidelines, which discuss the special circuit connections and
layout requirements that are needed for certain pins.
Power and Ground Recommendations
When connecting power to the AD9641, it is recommended
that two separate 1.8 V supplies be used. Use one supply for
analog (AVDD), and use a separate supply for the digital outputs
(DRVDD). For both AVDD and DRVDD, several different
decoupling capacitors should be used to cover both high and
low frequencies. Place these capacitors close to the point of entry
at the PCB level and close to the pins of the part, with minimal
trace length.
A single PCB ground plane should be sufficient when using the
AD9641. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance
is easily achieved.
Exposed Paddle Thermal Heat Slug Recommendations
It is mandatory that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance. A continuous, exposed
(no solder mask) copper plane on the PCB should mate to the
AD9641 exposed paddle, Pin 0.
The copper plane should have several vias to achieve the lowest
possible resistive thermal path for heat dissipation to flow through
the bottom of the PCB. These vias should be filled or plugged to
prevent solder wicking through the vias, which can compromise
the connection.
To maximize the coverage and adhesion between the ADC and
the PCB, a silkscreen should be overlaid to partition the continuous
plane on the PCB into several uniform sections. This provides
several tie points between the ADC and the PCB during the reflow
process. Using one continuous plane with no partitions guarantees
only one tie point between the ADC and the PCB. For detailed
information about packaging and PCB layout of chip scale
packages, see the AN-772 Application Note, A Design and
Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP), at www.analog.com.
VCM
The VCM pin should be decoupled to ground with a 0.1 μF
capacitor, as shown in Figure 50.
SPI Port
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices,
it may be necessary to provide buffers between this bus and the
AD9641 to keep these signals from transitioning at the converter
inputs during critical sampling periods.
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| AD9641BCPZ-155 | 制造商:Analog Devices 功能描述:14BIT 155MSPS ADC W/JESD204A - Trays 制造商:Analog Devices 功能描述:IC ADC 14BIT SRL 155MSPS 32LFCSP |
| AD9641BCPZ-80 | 功能描述:IC ADC 14BIT SRL 80MSPS 32LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
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