t
參數(shù)資料
型號(hào): AD9641-80KITZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 34/36頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD9641
設(shè)計(jì)資源: AD9641 Gerber Files
AD9641 80KITZ BOM
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 1
位數(shù): 14
采樣率(每秒): 80M
數(shù)據(jù)接口: 串行,SPI?
輸入范圍: 1.4 ~ 2.1 Vpp
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD9641
已供物品:
Data Sheet
AD9641
Rev. B | Page 7 of 36
TIMING SPECIFICATIONS
Table 5.
Parameter
Test Conditions
Limit
SYNC TIMING REQUIREMENTS
tSSYNC
SYNC to rising edge of CLK+ setup time
0.30 ns typ
tHSYNC
SYNC to rising edge of CLK+ hold time
0.30 ns typ
SPI TIMING REQUIREMENTS
tDS
Setup time between the data and the rising edge of SCLK
2 ns min
tDH
Hold time between the data and the rising edge of SCLK
2 ns min
tCLK
Period of the SCLK
40 ns min
tS
Setup time between CSB and SCLK
2 ns min
tH
Hold time between CSB and SCLK
2 ns min
tHIGH
SCLK pulse width high
10 ns min
tLOW
SCLK pulse width low
10 ns min
tEN_SDIO
Time required for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge
10 ns min
tDIS_SDIO
Time required for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge
10 ns min
Timing Diagrams
09
21
0-
00
2
DOUT+
SAMPLE N – 23
ENCODED INTO 2
8b/10b SYMBOLS
SAMPLE N – 22
ENCODED INTO 2
8b/10b SYMBOLS
SAMPLE N – 21
ENCODED INTO 2
8b/10b SYMBOLS
SAMPLE
N
N – 22
N – 23
N – 21
N – 20
N + 1
ANALOG
INPUT
SIGNAL
CLK+
CLK–
N – 1
CLK+
CLK–
DOUT–
Figure 2. Data Output Timing
SYNC
CLK+
tHSYNC
tSSYNC
09
21
0-
0
03
Figure 3. SYNC Input Timing Requirements
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