參數(shù)資料
型號： ADAU1382BCPZ
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQCC32
封裝： 5 X 5 MM, ROHS COMPLIANT, MO-220VHHD2, LFCSP-32
文件頁數(shù)： 21/84頁
文件大小： 1193K
代理商： ADAU1382BCPZ
ADAU1382
Rev. 0 | Page 28 of 84
Table 14 and Table 15 list the sampling rate divisions for
common base sampling rates.
Table 14. Base Sampling Rate Divisions for fS = 48 kHz
Base Sampling
Frequency
Sampling Rate Scaling
Sampling Rate
fS = 48 kHz
fS/1
48 kHz
fS/6
8 kHz
fS/4
12 kHz
fS/3
16 kHz
fS/2
24 kHz
fS/1.5
32 kHz
fS/0.5
96 kHz
Table 15. Base Sampling Rate Divisions for fS = 44.1 kHz
Base Sampling
Frequency
Sampling Rate Scaling
Sampling Rate
fS = 44.1 kHz
fS/1
44.1 kHz
fS/6
7.35 kHz
fS/4
11.025 kHz
fS/3
14.7 kHz
fS/2
22.05 kHz
fS/1.5
29.4 kHz
fS/0.5
88.2 kHz
PLL
The PLL uses the MCLK as a reference to generate the core
clock. PLL settings are set in Register 16386 (0x4002), PLL
control. Depending on the MCLK frequency, the PLL must be
set for either integer or fractional mode. The PLL can accept
input frequencies in the range of 11 MHz to 20 MHz.
All six bytes in the PLL control register must be written with a
single continuous write to the control port.
MCKI
÷ X
× (R + N/M)
TO PLL
CLOCK DIVIDER
08
42
7
-02
8
Figure 29. PLL Block Diagram
Integer Mode
Integer mode is used when the MCLK is an integer (R) multiple
of the PLL output (1024 × fS).
For example, if MCLK = 12.288 MHz and fS = 48 kHz, then
PLL Required Output = 1024 × 48 kHz = 49.152 MHz
R = 49.152 MHz/12.288 MHz = 4
In integer mode, the values set for N and M are ignored.
Fractional Mode
Fractional mode is used when the MCLK is a fractional
(R + (N/M)) multiple of the PLL output.
For example, if MCLK = 12 MHz and fS = 48 kHz, then
PLL Required Output = 1024 × 48 kHz = 49.152 MHz
R + (N/M) = 49.152 MHz/12 MHz = 4 + (12/125)
Common fractional PLL parameter settings for 44.1 kHz and
48 kHz sampling rates can be found in Table 16 and Table 17.
Table 16. Fractional PLL Parameter Settings for fS = 44.1 kHz1
MCLK
Input
(MHz)
Input
Divider
(X)
Integer
(R)
Denominator
(M)
Numerator
(N)
12
1
3
625
477
13
1
3
8125
3849
14.4
2
6
125
34
19.2
2
4
125
88
19.68
2
4
1025
604
19.8
2
4
1375
772
1 Desired core clock = 11.2896 MHz, PLL output = 45.1584 MHz.
Table 17. Fractional PLL Parameter Settings for fS = 48 kHz1
MCLK
Input
(MHz)
Input
Divider
(X)
Integer
(R)
Denominator
(M)
Numerator
(N)
12
1
4
125
12
13
1
3
1625
1269
14.4
2
6
75
62
19.2
2
5
25
3
19.68
2
4
205
204
19.8
2
4
825
796
1 Desired core clock = 12.288 MHz, PLL output = 49.152 MHz.
The PLL outputs a clock in the range of 41 MHz to 54 MHz,
which should be taken into account when calculating PLL
values and MCLK frequencies.
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