參數(shù)資料
型號(hào)： ADAU1382BCPZ
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQCC32
封裝： 5 X 5 MM, ROHS COMPLIANT, MO-220VHHD2, LFCSP-32
文件頁數(shù)： 65/84頁
文件大?。?/td> 1193K
代理商： ADAU1382BCPZ
ADAU1382
Rev. 0 | Page 68 of 84
Register 16426 (0x402A), DAC Control
Bits[7:6], Mono Mode
These bits control the output mode of the DAC. Setting these
bits to 00 outputs two distinct channels, left and right. Setting
these bits to 01 outputs the left input channel on both the left
and right outputs, and the right input channel is lost. Setting
these bits to 10 outputs the right input channel on both the left
and right outputs, and the left input channel is lost. Setting these
bits to 11 mixes the left and right input channels and outputs
the mixed mono signal on both the left and right outputs.
Bit 5, Invert Input Polarity
This bit applies a gain of 1, or a 180° phase shift, to the DAC
output signal.
Bit 2, DAC De-Emphasis Filter Enable
This bit enables a de-emphasis filter and should be used when a
preemphasized signal is input to the DACs.
Bits[1:0], DAC Enable
These bits allow the DACs to be individually enabled or disabled.
Disabling unused DACs can result in significant power savings.
Table 56. DAC Control Register
Bits
Description
Default
[7:6]
Mono mode
00
00: stereo output
01: both output left channel
10: both output right channel
11: both output left/right mix
5
Invert input polarity
0
0: normal
1: inverted
[4:3]
Reserved
2
DAC de-emphasis filter enable
0
0: disabled
1: enabled
[1:0]
DAC enable
00
00: both off
01: left on
10: right on
11: both on
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