參數(shù)資料
型號(hào)： ADAU1761BCPZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 20/92頁(yè)
文件大小： 0K
描述： IC SIGMADSP CODEC PLL 32LFCSP
設(shè)計(jì)資源： Stereo Digital Microphone Input Using ADAU1761 and ADMP421 (CN0078)
標(biāo)準(zhǔn)包裝： 5,000
系列： SigmaDSP®
類型： 音頻編解碼器
數(shù)據(jù)接口： 串行
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 是
電壓 - 電源，模擬： 1.8 V ~ 3.65 V
電壓 - 電源，數(shù)字： 1.63V ~ 3.65V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ
包裝： 帶卷 (TR)
配用： EVAL-ADAU1761Z-ND - BOARD EVAL FOR ADAU1761
ADAU1761
Rev. C | Page 27 of 92
SAMPLING RATES
The ADCs, DACs, and serial port share a common sampling
rate that is set in Register R17 (Converter Control 0 register,
Address 0x4017). The CONVSR[2:0] bits set the sampling rate
as a ratio of the base sampling frequency. The DSP sampling
rate is set in Register R57 (DSP sampling rate setting register,
Address 0x40EB) using the DSPSR[3:0] bits, and the serial port
sampling rate is set in Register R64 (serial port sampling rate
register, Address 0x40F8) using the SPSR[2:0] bits.
It is recommended that the sampling rates for the converters,
serial ports, and DSP be set to the same value, unless appropriate
compensation filtering is done within the DSP. Table 13 and
Table 14 list the sampling rate divisions for common base
sampling rates.
Table 13. 48 kHz Base Sampling Rate Divisions
Base Sampling
Frequency
Sampling Rate Scaling
Sampling Rate
fS/1
48 kHz
fS/6
8 kHz
fS/4
12 kHz
fS/3
16 kHz
fS/2
24 kHz
fS/1.5
32 kHz
fS = 48 kHz
fS/0.5
96 kHz
Table 14. 44.1 kHz Base Sampling Rate Divisions
Base Sampling
Frequency
Sampling Rate Scaling
Sampling Rate
fS/1
44.1 kHz
fS/6
7.35 kHz
fS/4
11.025 kHz
fS/3
14.7 kHz
fS/2
22.05 kHz
fS/1.5
29.4 kHz
fS = 44.1 kHz
fS/0.5
88.2 kHz
PLL
The PLL uses the MCLK as a reference to generate the core
clock. PLL settings are set in Register R1 (PLL control register,
Address 0x4002). Depending on the MCLK frequency, the PLL
must be set for either integer or fractional mode. The PLL can
accept input frequencies in the range of 8 MHz to 27 MHz.
All six bytes in the PLL control register must be written with a
single continuous write to the control port.
MCLK
÷ X
× (R + N/M)
TO PLL
CLOCK DIVIDER
07
68
0
-02
1
Figure 31. PLL Block Diagram
Integer Mode
Integer mode is used when the MCLK is an integer (R) multiple
of the PLL output (1024 × fS).
For example, if MCLK = 12.288 MHz and fS = 48 kHz, then
PLL required output = 1024 × 48 kHz = 49.152 MHz
R = 49.152 MHz/12.288 MHz = 4
In integer mode, the values set for N and M are ignored.
Fractional Mode
Fractional mode is used when the MCLK is a fractional
(R + (N/M)) multiple of the PLL output.
For example, if MCLK = 12 MHz and fS = 48 kHz, then
PLL required output = 1024 × 48 kHz = 49.152 MHz
R + (N/M) = 49.152 MHz/12 MHz = 4 + (12/125)
Common fractional PLL parameter settings for 44.1 kHz and
48 kHz sampling rates can be found in Table 16 and Table 17.
The PLL outputs a clock in the range of 41 MHz to 54 MHz,
which should be taken into account when calculating PLL
values and MCLK frequencies.
Table 15. PLL Control Register (Register R1, Address 0x4002)
Bits
Bit Name
Description
[47:32]
M[15:0]
Denominator of the fractional PLL: 16-bit binary number
0x00FD: M = 253 (default)
[31:16]
N[15:0]
Numerator of the fractional PLL: 16-bit binary number
0x000C: N = 12 (default)
[14:11]
R[3:0]
Integer part of PLL: four bits, only values 2 to 8 are valid
0010: R = 2 (default)
0011: R = 3
0100: R = 4
0101: R = 5
0110: R = 6
0111: R = 7
1000: R = 8
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