- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1895 > ADAU1761BCPZ-RL (Analog Devices Inc)IC SIGMADSP CODEC PLL 32LFCSP PDF資料下載
參數(shù)資料
| 型號： | ADAU1761BCPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 40/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SIGMADSP CODEC PLL 32LFCSP |
| 設(shè)計資源： | Stereo Digital Microphone Input Using ADAU1761 and ADMP421 (CN0078) |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 系列： | SigmaDSP® |
| 類型： | 音頻編解碼器 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 2 / 2 |
| 三角積分調(diào)變： | 是 |
| 電壓 - 電源，模擬： | 1.8 V ~ 3.65 V |
| 電壓 - 電源，數(shù)字： | 1.63V ~ 3.65V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADAU1761Z-ND - BOARD EVAL FOR ADAU1761 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁當(dāng)前第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁
ADAU1761
Rev. C | Page 45 of 92
DSP CORE
SIGNAL PROCESSING
The ADAU1761 is designed to provide all audio signal processing
functions commonly used in stereo or mono low power record
and playback systems. The signal processing flow is designed
using the SigmaStudio software, which allows graphical entry
and real-time control of all signal processing functions.
Many of the signal processing functions are coded using full,
56-bit, double-precision arithmetic data. The input and output
word lengths of the DSP core are 24 bits. Four extra headroom
bits are used in the processor to allow internal gains of up to
24 dB without clipping. Additional gains can be achieved by
initially scaling down the input signal in the DSP signal flow.
ARCHITECTURE
The DSP core consists of a simple 28-/56-bit multiply-accumulate
(MAC) unit with two sources: a data source and a coefficient
source. The data source can come from the data RAM, a ROM
table of commonly used constant values, or the audio inputs to
the core. The coefficient source can come from the parameter
RAM or from a ROM table of commonly used constant values.
The two sources are multiplied in a 28-bit fixed-point multiplier
and then the signal is input to the 56-bit adder; the result is usually
stored in one of three 56-bit accumulator registers. The accumu-
lators can be output from the core (in 28-bit format) or can
optionally be written back into the data or parameter RAMs.
COEFFICIENT SOURCE
(PARAMETER RAM,
ROM CONSTANTS)
DATA OPERATIONS
(ACCUMULATORS (3), dB CONVERSION,
BIT OPERATORS, BIT SHIFTER, ...)
DATA SOURCE
(DATA RAM,
ROM CONSTANTS,
AUDIO INPUTS)
OUTPUTS
TRUNCATOR
56
28
56
07
68
0-
0
67
Figure 67. Simplified DSP Core Architecture
PROGRAM COUNTER
The execution of instructions in the core is governed by a program
counter, which sequentially steps through the addresses of the
program RAM. The program counter starts every time that a
new audio frame is clocked into the core. SigmaStudio inserts
a jump-to-start command at the end of every program. The
program counter increments sequentially until it reaches this
command and then jumps to the program start address and
waits for the next audio frame to clock into the core.
FEATURES
The SigmaDSP core was designed specifically for audio processing
and therefore includes several features intended for maximizing
efficiency. These include hardware decibel conversion and audio-
specific ROM constants.
STARTUP
Before the DSPRUN bit is set or any settings are written to the
parameter RAM, the DSP core must be enabled by setting the
DSPEN bit in Register R61 (Address 0x40F5).
The following steps should be performed every time that a new
program is loaded to the SigmaDSP core, or any time that the
DSPRUN bit is disabled and reenabled.
1.
Set the DSPSR[3:0] bits in Register R57 (Address 0x40EB)
to 1111 (none).
2.
Set the DSPRUN bit in Register R62 (Address 0x40F6) to 0.
3.
Download the rest of the registers, the program RAM, and
the parameter RAM.
4.
Set the DSPRUN bit in Register R62 to 1.
5.
Set the DSPSR[3:0] bits in Register R57 to the operational
setting (default value is 0001).
Changing any register setting or RAM can cause pops and
clicks on the analog outputs. To avoid these pops and clicks,
mute the appropriate outputs using Register R29 to Register R32
(Address 0x4023 to Address 0x4026). Unmute the analog out-
puts after the startup procedure is completed.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADAU1781BCPZ-RL7 | IC SIGMADSP CODEC LN 32LFCSP |
| ADAU1961WBCPZ-R7 | IC STEREO AUD CODEC LP 32LFCSP |
| ADAU1966WBSTZ | IC DAC 24BIT SPI/I2C 192K 80LQFP |
| ADAV801ASTZ-REEL | IC CODEC AUDIO R-DVD 3.3V 64LQFP |
| ADAV803ASTZ | IC CODEC AUDIO R-DVD 3.3V 64LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADAU1772BCPZ | 功能描述:接口—CODEC Low Latency Noise and Power CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| ADAU1772BCPZ-R7 | 功能描述:接口—CODEC Low Latency Noise and Power CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| ADAU1772BCPZ-RL | 功能描述:接口—CODEC Low Latency Noise and Power CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| ADAU1777BCBZRL | 功能描述:LOW LATENCY NOISE AND POWER CODE 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):在售 類型:音頻 數(shù)據(jù)接口:I2C，SPI? 分辨率（位）:24 b ADC/DAC 數(shù):4 / 2 三角積分:無 信噪比，ADC/DAC（db）（典型值）:102 / 108 動態(tài)范圍，ADC/DAC（db）（典型值）:- 電壓 - 電源，模擬:1.71 V ~ 3.63 V 電壓 - 電源，數(shù)字:1.045 V ~ 1.98 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:36-WFBGA，WLCSP 供應(yīng)商器件封裝:36-WLCSP（3.77x3.20） 標(biāo)準(zhǔn)包裝:5,000 |
| ADAU1781 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Noise Stereo Codec with SigmaDSP Processing Core |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。