參數(shù)資料
型號(hào): ADAU1761BCPZ-RL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 81/92頁(yè)
文件大?。?/td> 0K
描述: IC SIGMADSP CODEC PLL 32LFCSP
設(shè)計(jì)資源: Stereo Digital Microphone Input Using ADAU1761 and ADMP421 (CN0078)
標(biāo)準(zhǔn)包裝: 5,000
系列: SigmaDSP®
類(lèi)型: 音頻編解碼器
數(shù)據(jù)接口: 串行
分辨率(位): 24 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
電壓 - 電源,模擬: 1.8 V ~ 3.65 V
電壓 - 電源,數(shù)字: 1.63V ~ 3.65V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-VQ
包裝: 帶卷 (TR)
配用: EVAL-ADAU1761Z-ND - BOARD EVAL FOR ADAU1761
ADAU1761
Rev. C | Page 82 of 92
R52 to R56: Watchdog Registers, 16,592 to 16,596 (0x40D0 to 0x40D4)
A program counter watchdog is used when the core does block processing (which can span several samples). The watchdog flags an error
if the program counter reaches a specific 24-bit value (ranging from 0x000000 to 0xFFFFFF) that is set in the register map. This value
consists of three consecutive 8-bit register locations. The error flag sends a high signal to one of the GPIO pins. The watchdog function
must be enabled by setting the DOGEN bit high in Register R52 (Address 0x40D0).
The watchdog error bit (DOGER) is the 1-bit watchdog error flag that can be sent to a GPIO pin, as described in Table 79. This error flag
can connect, for example, to an interrupt pin on a microcontroller in the system. The flag is reset when the DOGEN bit goes low. This
flag can also be read back over the control port from Register R56 (Address 0x40D4).
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x40D0
Reserved
DOGEN
0x40D1
DOG[23:16]
0x40D2
DOG[15:8]
0x40D3
DOG[7:0]
0x40D4
Reserved
DOGER
Table 81. Watchdog Registers
Address
Register
Decimal
Bit Name
Hex
Description
R52
16,592
0x40D0
DOGEN
Watchdog enable bit.
0 = disabled (default).
1 = enabled.
R53
16,593
0x40D1
DOG[23:16]
Watchdog value, Bits[23:16] (MSB).
R54
16,594
0x40D2
DOG[15:8]
Watchdog value, Bits[15:8].
R55
16,595
0x40D3
DOG[7:0]
Watchdog value, Bits[7:0].
DOG[23:16]
DOG[15:8]
DOG[7:0]
Hex Value
00000000
0x000000 (default)
11111111
0xFFFFFF
R56
16,596
0x40D4
DOGER
Watchdog error (read-only bit).
0 = no error (default).
1 = error.
R57: DSP Sampling Rate Setting, 16,619 (0x40EB)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
DSPSR[3:0]
Table 82. DSP Sampling Rate Setting Register
Bits
Bit Name
Description
[3:0]
DSPSR[3:0]
SigmaDSP core sampling rate. The DSP sampling rate is a ratio of the base sampling rate, fS. The base sampling rate
is determined by the operating frequency of the core clock. For most applications, the SigmaDSP core sampling
rate should equal the converter sampling rate (set using the CONVSR[2:0] bits in Register R17) and the serial
port sampling rate (set using the SPSR[2:0] bits in Register R64).
Setting
Sampling Rate
Base Sampling Rate (fS = 48 kHz)
0000
fS/0.5
96 kHz, base
0001
fS
48 kHz (default)
0010
fS/1.5
32 kHz
0011
fS/2
24 kHz
0100
fS/3
16 kHz
0101
fS/4
12 kHz
0110
fS/6
8 kHz
0111
Serial input data rate
1000
Serial output data rate
1111
None
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