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參數(shù)資料
| 型號： | ADAU1761BCPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 37/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SIGMADSP CODEC PLL 32LFCSP |
| 設計資源： | Stereo Digital Microphone Input Using ADAU1761 and ADMP421 (CN0078) |
| 標準包裝： | 5,000 |
| 系列： | SigmaDSP® |
| 類型： | 音頻編解碼器 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 2 / 2 |
| 三角積分調變： | 是 |
| 電壓 - 電源，模擬： | 1.8 V ~ 3.65 V |
| 電壓 - 電源，數(shù)字： | 1.63V ~ 3.65V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 32-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADAU1761Z-ND - BOARD EVAL FOR ADAU1761 |
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ADAU1761
Rev. C | Page 42 of 92
SERIAL DATA INPUT/OUTPUT PORTS
The flexible serial data input and output ports of the ADAU1761
can be set to accept or transmit data in 2-channel format or in
a 4-channel or 8-channel TDM stream to interface to external
ADCs or DACs. Data is processed in twos complement, MSB
first format. The left channel data field always precedes the right
channel data field in 2-channel streams. In TDM mode, Slot 0
to Slot 3 are in the first half of the audio frame, and Slot 4 to
Slot 7 are in the second half of the frame. The serial modes and
the position of the data in the frame are set in Register R15 to
Register R18 (serial port and converter control registers,
Address 0x4015 to Address 0x4018).
If the PLL of the ADAU1761 is not used, the serial data clocks
must be synchronous with the ADAU1761 master clock input.
The LRCLK and BCLK pins are used to clock both the serial
input and output ports. The ADAU1761 can be set as the master
or the slave in a system. Because there is only one set of serial
data clocks, the input and output ports must always be both
master or both slave.
Register R15 and Register R16 (serial port control registers,
Address 0x4015 and Address 0x4016) allow control of clock
polarity and data input modes. The valid data formats are I2S,
left-justified, right-justified (24-/20-/18-/16-bit), and TDM. In
all modes except for the right-justified modes, the serial port
inputs an arbitrary number of bits up to a limit of 24. Extra bits
do not cause an error, but they are truncated internally.
The serial port can operate with an arbitrary number of BCLK
transitions in each LRCLK frame. The LRCLK in TDM mode
can be input to the ADAU1761 either as a 50% duty cycle clock
or as a bit-wide pulse.
When the LRCLK is set as a pulse, a 47 pF capacitor should be
connected between the LRCLK pin and ground (see Figure 57).
This capacitor is necessary in both master and slave modes to
properly align the LRCLK signal to the serial data stream.
07
68
0-
0
71
47pF
LRCLK
ADAU1761
BCLK
Figure 57. LRCLK Capacitor Alignment, TDM Pulse Mode
In TDM 8 mode, the ADAU1761 can be a master for fS up to
48 kHz. Table 24 lists the modes in which the serial output port
can function.
Table 24. Serial Output Port Master/Slave Mode Capabilities
fS
2-Channel Modes (I2S, Left-
Justified, Right-Justified)
8-Channel TDM
48 kHz
Master and slave
96 kHz
Master and slave
Slave
Table 25 describes the proper configurations for standard audio
data formats.
Table 25. Data Format Configurations
Format
LRCLK Polarity (LRPOL)
LRCLK Mode
(LRMOD)
BCLK Polarity
(BPOL)
BCLK Cycles/Audio
Frame (BPF[2:0])
Data Delay from LRCLK
Edge (LRDEL[1:0])
I2S
(see Figure 58)
Frame begins on falling edge
50% duty cycle
Data changes
on falling edge
32 to 64
Delayed from LRCLK edge
by 1 BCLK
Left-Justified (see
Frame begins on rising edge
50% duty cycle
Data changes
on falling edge
32 to 64
Aligned with LRCLK edge
Right-Justified
(see Figure 60)
Frame begins on rising edge
50% duty cycle
Data changes
on falling edge
32 to 64
Delayed from LRCLK edge
by 8 or 16 BCLKs
TDM with Clock
(see Figure 61)
Frame begins on falling edge
50% duty cycle
Data changes
on falling edge
64 to 256
Delayed from start of word
clock by 1 BCLK
TDM with Pulse
(see Figure 62)
Frame begins on rising edge
Pulse
Data changes
on falling edge
64 to 256
Delayed from start of word
clock by 1 BCLK
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADAU1772BCPZ | 功能描述:接口—CODEC Low Latency Noise and Power CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| ADAU1772BCPZ-R7 | 功能描述:接口—CODEC Low Latency Noise and Power CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| ADAU1772BCPZ-RL | 功能描述:接口—CODEC Low Latency Noise and Power CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| ADAU1777BCBZRL | 功能描述:LOW LATENCY NOISE AND POWER CODE 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):在售 類型:音頻 數(shù)據(jù)接口:I2C，SPI? 分辨率（位）:24 b ADC/DAC 數(shù):4 / 2 三角積分:無 信噪比，ADC/DAC（db）（典型值）:102 / 108 動態(tài)范圍，ADC/DAC（db）（典型值）:- 電壓 - 電源，模擬:1.71 V ~ 3.63 V 電壓 - 電源，數(shù)字:1.045 V ~ 1.98 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:36-WFBGA，WLCSP 供應商器件封裝:36-WLCSP（3.77x3.20） 標準包裝:5,000 |
| ADAU1781 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Noise Stereo Codec with SigmaDSP Processing Core |
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