參數(shù)資料
型號: ADAU1761BCPZ-RL
廠商: Analog Devices Inc
文件頁數(shù): 78/92頁
文件大小: 0K
描述: IC SIGMADSP CODEC PLL 32LFCSP
設(shè)計資源: Stereo Digital Microphone Input Using ADAU1761 and ADMP421 (CN0078)
標(biāo)準(zhǔn)包裝: 5,000
系列: SigmaDSP®
類型: 音頻編解碼器
數(shù)據(jù)接口: 串行
分辨率(位): 24 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
電壓 - 電源,模擬: 1.8 V ~ 3.65 V
電壓 - 電源,數(shù)字: 1.63V ~ 3.65V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-VQ
包裝: 帶卷 (TR)
配用: EVAL-ADAU1761Z-ND - BOARD EVAL FOR ADAU1761
ADAU1761
Rev. C | Page 8 of 92
TYPICAL CURRENT CONSUMPTION
Master clock = 12.288 MHz, input sample rate = 48 kHz, input tone = 1 kHz, normal power management settings, ADC input @ 1 dBFS,
DAC input @ 0 dBFS. For total power consumption, add the IOVDD current listed in Table 2.
Table 3.
Operating Voltage
Audio Path
Clock Generation
Typical AVDD Current
Consumption (mA)
Direct MCLK
5.24
Record stereo differential to ADC
Integer PLL
6.57
Direct MCLK
5.55
AVDD = IOVDD = 3.3 V
DAC stereo playback to line output (10 kΩ)
Integer PLL
6.90
Direct MCLK
55.5
DAC stereo playback to headphone (16 Ω)
Integer PLL
56.8
Direct MCLK
30.9
DAC stereo playback to headphone (32 Ω)
Integer PLL
32.25
Direct MCLK
56.75
DAC stereo playback to capless headphone (32 Ω)
Integer PLL
58
Direct MCLK
1.9
Record aux stereo bypass to line output (10 kΩ)
Integer PLL
3.3
Direct MCLK
4.25
Record stereo differential to ADC
Integer PLL
5.55
Direct MCLK
4.7
AVDD = IOVDD = 1.8 V
DAC stereo playback to line output (10 kΩ)
Integer PLL
5.7
Direct MCLK
30.81
DAC stereo playback to headphone (16 Ω)
Integer PLL
32
Direct MCLK
18.3
DAC stereo playback to headphone (32 Ω)
Integer PLL
19.5
Direct MCLK
32.6
DAC stereo playback to capless headphone (32 Ω)
Integer PLL
33.7
Direct MCLK
1.9
Record aux stereo bypass to line output (10 kΩ)
Integer PLL
3.07
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