fS)
參數(shù)資料
型號(hào)： ADAV803ASTZ-REEL
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 21/60頁(yè)
文件大?。?/td> 0K
描述： IC CODEC AUDIO R-DVD 3.3V 64LQFP
標(biāo)準(zhǔn)包裝： 1,500
類(lèi)型： 音頻編解碼器
數(shù)據(jù)接口： 串行
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 無(wú)
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 102 / 101
電壓 - 電源，模擬： 3 V ~ 3.6 V
電壓 - 電源，數(shù)字： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 帶卷 (TR)
配用： EVAL-ADAV803EBZ-ND - BOARD EVALUATION FOR ADAV803
ADAV803
Rev. A | Page 28 of 60
04
75
6-
0
50
REG 0x76
BITS[4:2]
DIR PLL(512 ×
fS)
DIR PLL(256 ×
fS)
PLLINT1
PLLINT2
MCLKI
XIN
ICLK1
ICLK2
PLL CLOCK
REG 0x06
BITS[5:4]
MCLK
ADC
OUTPUT
PORT
OLRCLK
OBCLK
OSDATA
REG 0x76
BITS[7:5]
DIR PLL(512 ×
fS)
DIR PLL(256 ×
fS)
PLLINT1
PLLINT2
MCLKI
XIN
ICLK1
ICLK2
PLL CLOCK
REG 0x04
BITS[4:3]
MCLK
DAC
INPUT
PORT
ILRCLK
IBCLK
ISDATA
REG 0x77
BITS[4:3]
REG 0x00
BITS[3:2]
REG 0x00
BITS[1:0]
REG 0x00
BITS[4:5]
REG 0x76
BITS[1:0]
MCLKI
XIN
PLLINT1
PLLINT2
ICLK1
ICLK2
DIR PLL(512 ×
fS)
DIR PLL(256 ×
fS)
REG 0x00
BITS[7:6]
MCLKI
XIN
PLLINT1
PLLINT2
DIVIDER
SRC
MCLK
Figure 50. SPORT Clocking Scheme
Care should be taken to ensure that the clock rate is appropriate
for whatever block is connected to the serial port. For example,
if the ADC is running from the MCLKI input at 256 × fS, then
the master clock for the SPORT should also run from the
MCLKI input to ensure that the ADC and serial port are
synchronized.
The SPORTs can be set to transmit or receive data in I2S, left-
justified or right-justified formats with different word lengths
by programming the appropriate bits in the playback register,
auxiliary input port register, record register, and auxiliary
output port-control register. Figure 51 is a timing diagram of
the serial data port formats.
Clocking Scheme
The ADAV803 provides a flexible choice of on-chip and off-
chip clocking sources. The on-chip oscillator with dual PLLs is
intended to offer complete system clocking requirements for
use with available MPEG encoders, decoders, or a combination
of codecs. The oscillator function is designed for generation of a
27 MHz video clock from a 27 MHz crystal connected between
the XIN and XOUT pins. Capacitors must also be connected
between these pins and DGND, as shown in Figure 35. The
capacitor values should be specified by the crystal manufacturer.
A square wave version of the crystal clock is output on the
MCLKO pin. If the system has a 27 MHz clock available, this
clock can be connected directly to the XIN pin.
04
75
6-
05
1
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LSB
LEFT CHANNEL
RIGHT CHANNEL
LEFT CHANNEL
RIGHT CHANNEL
MSB
RIGHT-JUSTIFIED MODE — SELECT NUMBER OF BITS PER CHANNEL
I2S MODE — 16 BITS TO 24 BITS PER CHANNEL
LEFT-JUSTIFIED MODE — 16 BITS TO 24 BITS PER CHANNEL
Figure 51. Serial Data Modes
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