參數(shù)資料
型號： ADAV803ASTZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 36/60頁
文件大?。?/td> 0K
描述： IC CODEC AUDIO R-DVD 3.3V 64LQFP
標(biāo)準(zhǔn)包裝： 1,500
類型： 音頻編解碼器
數(shù)據(jù)接口： 串行
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 無
動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 102 / 101
電壓 - 電源，模擬： 3 V ~ 3.6 V
電壓 - 電源，數(shù)字： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 帶卷 (TR)
配用： EVAL-ADAV803EBZ-ND - BOARD EVALUATION FOR ADAV803
ADAV803
Rev. A | Page 41 of 60
Receiver Error—Address 0011000 (0x18)
Table 61. Receiver Error Register (Read-Only) Bit Map
7
6
5
4
3
2
1
0
RxValidity
Emphasis
NonAudio
NonAudio Preamble
CRCError
NoStream
BiPhase/Parity
Lock
Table 62. Receiver Error Register (Read-Only) Bit Descriptions
Bit Name
Description
RxValidity
This is the VALIDITY bit in the AES3 received stream.
Emphasis
This bit is set if the audio data is pre-emphasized. Once it has been read, it remains high and does not generate an
interrupt unless it changes state.
NonAudio
This bit is set when Channel Status Bit 1 (nonaudio) is set. Once it has been read, it does not generate another interrupt
unless the data becomes audio or the type of nonaudio data changes.
NonAudio
Preamble
This bit is set if the audio data is nonaudio due to the detection of a preamble. The nonaudio preamble type register
indicates what type of preamble was detected. Once read, it remains in its state and does not generate an interrupt
unless it changes state.
CRCError
This bit is the error flag for the channel status CRCError check. This bit does not clear until the receiver error register is read.
NoStream
This bit is set if there is no AES3/S/PDIF stream present at the AES3/S/PDIF receiver. Once read, it remains high and does
not generate an interrupt unless it changes state.
BiPhase/Parity
This bit is set if a biphase or parity error occurred in the AES3/S/PDIF stream. This bit is not cleared until the register is read.
Lock
This bit is set if the PLL has locked or cleared when the PLL loses lock. Once read, it remains in its state and does not
generate an interrupt unless it changes state.
Receiver Error Mask—Address 0011001 (0x19)
Table 63. Receiver Error Mask Register Bit Map
7
6
5
4
3
2
1
0
RxValidity
Mask
Emphasis
Mask
NonAudio
Mask
NonAudio Preamble
Mask
CRCError
Mask
NoStream
Mask
BiPhase/Parity
Mask
Lock
Mask
Table 64. Receiver Error Mask Register Bit Descriptions
Bit Name
Description
RxValidity Mask
Masks the RxValidity bit from generating an interrupt.
0 = RxValidity bit does not generate an interrupt.
1 = RxValidity bit generates an interrupt.
Emphasis Mask
Masks the Emphasis bit from generating an interrupt.
0 = Emphasis bit does not generate an interrupt.
1 = Emphasis bit generates an interrupt.
NonAudio Mask
Masks the NonAudio bit from generating an interrupt.
0 = NonAudio bit does not generate an interrupt.
1 = NonAudio bit generates an interrupt.
NonAudio Preamble Mask
Masks the NonAudio preamble bit from generating an interrupt.
0 = NonAudio preamble bit does not generate an interrupt.
1 = NonAudio preamble bit generates an interrupt.
CRCError Mask
Masks the CRCError bit from generating an interrupt.
0 = CRCError bit does not generate an interrupt.
1 = CRCError bit generates an interrupt.
NoStream Mask
Masks the NoStream bit from generating an interrupt.
0 = NoStream bit does not generate an interrupt.
1 = NoStream bit generates an interrupt.
BiPhase/Parity Mask
Masks the BiPhase/Parity bit from generating an interrupt.
0 = BiPhase/Parity bit does not generate an interrupt.
1 = BiPhase/Parity bit generates an interrupt.
Lock Mask
Masks the Lock bit from generating an interrupt.
0 = Lock bit does not generate an interrupt.
1 = Lock bit generates an interrupt.
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