參數(shù)資料
型號(hào)： ADAV803ASTZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 30/60頁(yè)
文件大小： 0K
描述： IC CODEC AUDIO R-DVD 3.3V 64LQFP
標(biāo)準(zhǔn)包裝： 1,500
類(lèi)型： 音頻編解碼器
數(shù)據(jù)接口： 串行
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 無(wú)
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 102 / 101
電壓 - 電源，模擬： 3 V ~ 3.6 V
電壓 - 電源，數(shù)字： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 帶卷 (TR)
配用： EVAL-ADAV803EBZ-ND - BOARD EVALUATION FOR ADAV803
ADAV803
Rev. A | Page 36 of 60
Receiver Configuration 2—Address 0001010 (0x0A)
Table 33. Receiver Configuration 2 Register Bit Map
7
6
5
4
3
2
1
0
RxMUTE
SP_PLL
SP_PLL_ SEL1
SP_PLL_ SEL0
Reserved
NO NONAUDIO
NO_VALIDITY
Table 34. Receiver Configuration 2 Register Bit Descriptions
Bit Name
Description
RxMUTE
Hard-mutes the audio output for the AES3/S/PDIF receiver.
0 = AES3/S/PDIF receiver is not muted.
1 = AES3/S/PDIF receiver is muted.
SP_PLL
AES3/S/PDIF receiver PLL accepts a left/right clock from one of the four serial ports as the PLL reference clock.
0 = Left/right clock generated from the AES3/S/PDIF preambles is the reference clock to the PLL.
1 = Left/right clock from one of the serial ports is the reference clock to the PLL.
SP_PLL_SEL[1:0]
Selects one of the four serial ports as the reference clock to the PLL when SP_PLL is set.
00 = Playback port is selected.
01 = Auxiliary input port is selected.
10 = Record port is selected.
11 = Auxiliary output port is selected.
NO NONAUDIO
When the NO NONAUDIO bit is set, data from the AES3/S/PDIF receiver is not allowed into the sample rate converter
(SRC). If the NO NONAUDIO data is due to DTS, AAC, and so on, as defined by the IEC61937 standard, then the data
from the AES3/S/PDIF receiver is not allowed into the SRC regardless of the state of this bit.
0 = AES3/S/PDIF receiver data is sent to the SRC.
1 = Data from the AES3/S/PDIF receiver is not allowed into the SRC, if the NO NONAUDIO bit is set.
NO_VALIDITY
When the NO_VALIDITY bit is set, data from the AES3/S/PDIF receiver is not allowed into the SRC.
0 = AES3/S/PDIF receiver data is sent to the SRC.
1 = Data from the AES3/S/PDIF receiver is not allowed into the SRC, if the NO_VALIDITY bit is set.
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