參數(shù)資料
型號： ADAV803ASTZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 60/60頁
文件大小： 0K
描述： IC CODEC AUDIO R-DVD 3.3V 64LQFP
標(biāo)準(zhǔn)包裝： 1,500
類型： 音頻編解碼器
數(shù)據(jù)接口： 串行
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 無
動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 102 / 101
電壓 - 電源，模擬： 3 V ~ 3.6 V
電壓 - 電源，數(shù)字： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 帶卷 (TR)
配用： EVAL-ADAV803EBZ-ND - BOARD EVALUATION FOR ADAV803
ADAV803
Rev. A | Page 9 of 60
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC
VO
U
T
L
NC
VO
U
T
R
OA
U
X
S
D
A
TA
IA
UX
L
RCL
K
IA
U
X
B
C
LK
IA
U
X
S
D
A
TA
ZEROL/INT
ZEROR
DVDD
DGND
ADVDD
ADGND
PLL_LF2
PLL_LF1
PLL_GND
PLL_VDD
DGND
SYSCLK1
SYSCLK2
SYSCLK3
XIN
XOUT
39
38
37
41
40
MCLKO
MCLKI
DVDD
DGND
36
35
34
33
42
43
44
45
46
47
48
17 18 19 20 21 22 23 24
IL
R
C
L
K
IBCL
K
IS
D
A
TA
OL
R
C
L
K
O
BCL
K
OS
D
A
TA
DI
RI
N
OD
V
D
OD
GN
D
DI
T
O
U
T
O
A
UX
L
RCL
K
OA
U
X
B
C
L
K
1
2
3
4
5
6
7
8
9
10
11
12
64 63 62 61 60 59 58
CAP
L
N
CAP
L
P
AG
ND
CAP
R
P
CAP
RN
AV
D
AG
ND
VR
EF
AG
ND
FI
LTD
AG
ND
AV
D
VINR
VINL
AGND
AVDD
DIR_LF
DIR_GND
DIR_VDD
RESET
AD0
SDA
SCL
AD1
13
14
15
16
25 26 27
31
30
29
28
32
57 56 55 54 53 52 51 50 49
ADAV803
TOP VIEW
(Not to Scale)
04
75
6-
00
2
PIN 1
INDICATOR
NC = NO CONNECT
Figure 2. ADAV803 Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
I/O
Description
1
VINR
I
Analog Audio Input, Right Channel.
2
VINL
I
Analog Audio Input, Left Channel.
3
AGND
Analog Ground.
4
AVDD
Analog Voltage Supply.
5
DIR_LF
DIR Phase-Locked Loop (PLL) Filter Pin.
6
DIR_GND
Supply Ground for DIR Analog Section. This pin should be connected to AGND.
7
DIR_VDD
Supply for DIR Analog Section. This pin should be connected to AVDD.
8
RESET
I
Asynchronous Reset Input (Active Low).
9
AD0
I
I2C Address LSB.
10
SDA
I/O
Data Input/Output of I2C-Compatible Control Interface.
11
SCL
I
Clock Input of I2C Compatible Control Interface.
12
AD1
I
I2C Address MSB.
13
ZEROL/INT
O
Left Channel (Output) Zero Flag or Interrupt (Output) Flag. The function of this pin is determined by
the INTRPT bit in DAC Control Register 4.
14
ZEROR
O
Right Channel (Output) Zero Flag.
15
DVDD
Digital Voltage Supply.
16
DGND
Digital Ground.
17
ILRCLK
I/O
Sampling Clock (LRCLK) of Playback Digital Input Port.
18
IBCLK
I/O
Serial Clock (BCLK) of Playback Digital Input Port.
19
ISDATA
I
Data Input of Playback Digital Input Port.
20
OLRCLK
I/O
Sampling Clock (LRCLK) of Record Digital Output Port.
21
OBCLK
I/O
Serial Clock (BCLK) of Record Digital Output Port.
22
OSDATA
O
Data Output of Record Digital Output Port.
23
DIRIN
I
Input to Digital Input Receiver (S/PDIF).
24
ODVDD
Interface Digital Voltage Supply.
25
ODGND
Interface Digital Ground.
26
DITOUT
O
S/PDIF Output from DIT.
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