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參數(shù)資料
| 型號： | ADAV803ASTZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 37/60頁 |
| 文件大小： | 0K |
| 描述： | IC CODEC AUDIO R-DVD 3.3V 64LQFP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 音頻編解碼器 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 2 / 2 |
| 三角積分調(diào)變： | 無 |
| 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： | 102 / 101 |
| 電壓 - 電源，模擬： | 3 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADAV803EBZ-ND - BOARD EVALUATION FOR ADAV803 |
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ADAV803
Rev. A | Page 42 of 60
Sample Rate Converter Error—Address 0011010 (0x1A)
Table 65. Sample Rate Converter Error Register (Read-Only) Bit Map
7
6
5
4
3
2
1
0
Reserved
TOO_SLOW
OVRL
OVRR
MUTE_IND
Table 66. Sample Rate Converter Error Register (Read-Only) Bit Descriptions
Bit Name
Description
TOO_SLOW
This bit is set when the clock to the SRC is too slow, that is, there are not enough clock cycles to complete the
internal convolution.
OVRL
This bit is set when the left output data of the sample rate converter has gone over the full-scale range and has been
clipped. This bit is not cleared until the register is read.
OVRR
This bit is set when the right output data of the sample rate converter has gone over the full-scale range and has
been clipped. This bit is not cleared until the register is read.
MUTE_IND
Mute indicated. This bit is set when the SRC is in fast mode and clicks or pops can be heard in the SRC output data.
The output of the SRC can be muted, if required, until the SRC is in slow mode. Once read, this bit remains in its state
and does not generate an interrupt until it has changed state.
Sample Rate Converter Error Mask—Address 0011011 (0x1B)
Table 67. Sample Rate Converter Error Mask Register Bit Map
7
6
5
4
3
2
1
0
Reserved
OVRL Mask
OVRR Mask
MUTE_IND MASK
Table 68. Sample Rate Converter Error Mask Register Bit Descriptions
Bit Name
Description
OVRL Mask
Masks the OVRL from generating an interrupt.
0 = OVRL bit does not generate an interrupt.
1 = OVRL bit generates an interrupt.
OVRR Mask
Masks the OVRR from generating an interrupt.
0 = OVRR bit does not generate an interrupt.
1 = OVRR bit generates an interrupt. Reserved.
MUTE_IND MASK
Masks the MUTE_IND from generating an interrupt.
0 = MUTE_IND bit does not generate an interrupt.
1 = MUTE_IND bit generates an interrupt.
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