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參數(shù)資料
| 型號： | ADAV803ASTZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC AUDIO R-DVD 3.3V 64LQFP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 音頻編解碼器 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 2 / 2 |
| 三角積分調(diào)變： | 無 |
| 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： | 102 / 101 |
| 電壓 - 電源，模擬： | 3 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADAV803EBZ-ND - BOARD EVALUATION FOR ADAV803 |
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ADAV803
Rev. A | Page 30 of 60
INTERFACE CONTROL
The ADAV803 has a dedicated control port to allow the internal
registers of the ADAV803 to be accessed. Each of the internal
registers is eight bits wide. Where bits are described as reserved
(RES), these bits should be programmed as zero.
I2C INTERFACE
The I2C interface of the ADAV803 is a 2-wire interface
consisting of a clock line, SCL, and a data line, SDA. SDA is
bidirectional; the ADAV803 drives SDA to either acknowledge
the master, ACK, or send data during a read operation. The
SDA pin for the I2C port is an open-drain collector that requires
a 1 kΩ pull-up resistor. A write or read access occurs when the
SDA line is pulled low while the SCL line is high, indicated by
START in the timing diagrams. SDA is allowed to change only
when SCL is low, except when a start or stop condition occurs,
both standard (100 kbps) and fast (400 kbps) modes as defined
by the I2C standards.
The first eight bits of the access consist of the device address
and the R/W bit. The device address consists of an internal
built-in address (0b00100) and two address pins, AD1 and
AD0. The two address pins allow up to four ADAV803s to be
used in a system.
Initiating a write operation to the ADAV803 involves sending a
start condition and then sending the device address with the
R/W set low. The ADAV803 responds by issuing an ACK to
indicate that it has been addressed. The user then sends a
second frame telling the ADAV803 which register is required to
be written to. The 7-bit register address is left-shifted to make
the eight bits that the frame requires. Another ACK is issued by
the ADAV803. Finally, the user can send another frame with the
eight data bits required to be written to the register. A third
ACK is issued by the ADAV803, after which the user can send a
stop condition to complete the data transfer.
A read operation requires that the user first write to the
ADAV803 to point to the correct register and then read the
data. This is achieved by sending a start condition followed by
the device address frame, with R/W low, and then the register
address frame. Following the ACK from the ADAV803, the user
must issue a repeated start condition. This is identical to a start
condition. The next frame is the device address with R/W set
high. On the next frame, the ADAV803 outputs the register data
on the SDA line. A stop condition completes the read operation.
ing from the DAC left volume register (Address 0b1101000).
0
01
0
1
0
1
0
X
04
75
6-
0
53
SCK
SDA
AD1
AD0
R/W
START BY
MASTER
ACK. BY
ADAV803
ACK. BY
ADAV803
ACK. BY
ADAV803
STOP BY
MASTER
FRAME 1
CHIP ADDRESS BYTE
SCK
(CONTINUED)
SDA
(CONTINUED)
FRAME 2
REGISTER ADDRESS BYTE
FRAME 3
DATA BYTE TO
ADAV803
D7
D6
D5
D4
D3
D2
D1
D0
Figure 53. Writing to the DAC Left Volume Register in I2C
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