Tie or pull unused inputs to VDD or GND, except for the " />
參數(shù)資料
型號(hào)： ADSP-21160NKBZ-100
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 2/48頁(yè)
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 32BIT 400-BGA
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： 主機(jī)接口，連接端口，串行端口
時(shí)鐘速率： 100MHz
非易失內(nèi)存： 外部
芯片上RAM： 512kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.90V
工作溫度： 0°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 400-BBGA
供應(yīng)商設(shè)備封裝： 400-PBGA（27x27）
包裝： 托盤
ADSP-21160N
–10–
REV. 0
Tie or pull unused inputs to VDD or GND, except for the
following:
ADDR31–0, DATA63–0, PAGE, BRST, CLKOUT
(ID2 – 0 = 00x) (Note: These pins have a logic-level hold
circuit enabled on the ADSP-21160N DSP with ID2 – 0
= 00x.)
PA, ACK, MS3–0, RDx, WRx, CIF, DMARx, DMAGx
(ID2 – 0 = 00x) (Note: These pins have a pull-up enabled
on the ADSP-21160N DSP with ID2 – 0 = 00x.)
LxCLK, LxACK, LxDAT7–0 (LxPDRDE = 0) (Note:
See Link Port Buffer Control Register Bit definitions in
the ADSP-21160 DSP Hardware Reference.)
DTx, DRx, TCLKx, RCLKx, EMU, TMS, TRST, TDI
(Note: These pins have a pull-up.)
The following symbols appear in the Type column of Table 2:
A = Asynchronous, G = Ground, I = Input, O = Output,
P=Power Supply, S=Synchronous, (A/D)=Active Drive,
(O/D) = Open Drain, and T = Three-State (when
SBTS is
asserted, or when the ADSP-21160N is a bus slave).
Table 2. Pin Function Descriptions
Pin
Type
Function
ADDR31–0
I/O/T
External Bus Address. The ADSP-21160N outputs addresses for external memory and
peripherals on these pins. In a multiprocessor system, the bus master outputs addresses
for read/writes of the internal memory or IOP registers of other ADSP-21160Ns. The
ADSP-21160N inputs addresses when a host processor or multiprocessing bus master
is reading or writing its internal memory or IOP registers. A keeper latch on the DSP’s
ADDR31–0 pins maintains the input at the level it was last driven (only enabled on the
ADSP-21160N with ID2–0 = 00x).
DATA63–0
I/O/T
External Bus Data. The ADSP-21160N inputs and outputs data and instructions on
these pins. Pull-up resistors on unused DATA pins are not necessary. A keeper latch on
the DSP’s DATA63-0 pins maintains the input at the level it was last driven (only enabled
on the ADSP-21160N with ID2–0 = 00x).
MS3–0
O/T
Memory Select Lines. These outputs are asserted (low) as chip selects for the corre-
sponding banks of external memory. Memory bank size must be defined in the SYSCON
control register. The
MS3–0 outputs are decoded memory address lines. In asyn-
chronous access mode, the
MS3–0 outputs transition with the other address outputs.
In synchronous access modes, the
MS3–0 outputs assert with the other address lines;
however, they deassert after the first CLKIN cycle in which ACK is sampled asserted.
MS3–0 has a 20 k
internal pull-up resistor that is enabled on the ADSP-21160N with
ID2–0 = 00x.
RDL
I/O/T
Memory Read Low Strobe.
RDL is asserted whenever ADSP-21160N reads from the
low word of external memory or from the internal memory of other ADSP-21160Ns.
External devices, including other ADSP-21160Ns, must assert
RDL for reading from
the low word of ADSP-21160N internal memory. In a multiprocessing system,
RDL is
driven by the bus master.
RDL has a 20 k
internal pull-up resistor that is enabled on
the ADSP-21160N with ID2–0 = 00x.
RDH
I/O/T
Memory Read High Strobe.
RDH is asserted whenever ADSP-21160N reads from the
high word of external memory or from the internal memory of other ADSP-21160Ns.
External devices, including other ADSP-21160Ns, must assert
RDH for reading from
the high word of ADSP-21160N internal memory. In a multiprocessing system,
RDH
is driven by the bus master.
RDH has a 20 k
internal pull-up resistor that is enabled
on the ADSP-21160N with ID2–0 = 00x.
WRL
I/O/T
Memory Write Low Strobe.
WRL is asserted when ADSP-21160N writes to the low
word of external memory or internal memory of other ADSP-21160Ns. External devices
must assert
WRL for writing to ADSP-21160N’s low word of internal memory. In a
multiprocessing system,
WRL is driven by the bus master. WRL has a 20 k
internal
pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x.
WRH
I/O/T
Memory Write High Strobe.
WRH is asserted when ADSP-21160N writes to the high
word of external memory or internal memory of other ADSP-21160Ns. External devices
must assert
WRH for writing to ADSP-21160N’s high word of internal memory. In a
multiprocessing system,
WRH is driven by the bus master. WRH has a 20 k
internal
pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x.
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