V
參數(shù)資料
型號(hào): ADSP-21160NKBZ-100
廠商: Analog Devices Inc
文件頁(yè)數(shù): 6/48頁(yè)
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 32BIT 400-BGA
產(chǎn)品培訓(xùn)模塊: SHARC Processor Overview
標(biāo)準(zhǔn)包裝: 1
系列: SHARC®
類(lèi)型: 浮點(diǎn)
接口: 主機(jī)接口,連接端口,串行端口
時(shí)鐘速率: 100MHz
非易失內(nèi)存: 外部
芯片上RAM: 512kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.90V
工作溫度: 0°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 400-BBGA
供應(yīng)商設(shè)備封裝: 400-PBGA(27x27)
包裝: 托盤(pán)
ADSP-21160N
–14–
REV. 0
SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
C Grade
K Grade
Unit
Parameter
Min
Max
Min
Max
VDDINT
Internal (Core) Supply Voltage
1.8
2.0
1.8
2.0
V
AVDD
Analog (PLL) Supply Voltage
1.8
2.0
1.8
2.0
V
VDDEXT
External (I/O) Supply Voltage
3.13
3.47
3.13
3.47
V
TCASE
Case Operating Temperature
1
1 See Environmental Conditions on Page 42 for information on thermal specifications.
– 40
+ 100
0
85
C
VIH1
High Level Input Voltage,
2 @ V
DDEXT =Max
2 Applies to input and bidirectional pins: DATA63–0, ADDR31–0,
RDx, WRx, ACK, SBTS, IRQ2–0, FLAG3–0, HBG, CS, DMAR1, DMAR2, BR6–1,
ID2–0, RPBA,
PA, BRST, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1,
TCLK0, TCLK1, RCLK0, RCLK1.
2.0
VDDEXT+0.5
2.0
VDDEXT+0.5
V
VIH2
High Level Input Voltage,
3 @ V
DDEXT =Max
3 Applies to input pins: CLKIN,
RESET, TRST.
2.0
VDDEXT+0.5
2.0
VDDEXT+0.5
V
VIL
Low Level Input Voltage,
2, 3 @ V
DDEXT = Min
– 0.5
+ 0.8
– 0.5
+ 0.8
V
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS
Parameter
Test Conditions
Min
Max
Unit
VOH
High Level Output Voltage
1
1 Applies to output and bidirectional pins: DATA63–0, ADDR31–0,
MS3–0, RDx, WRx, PAGE, CLKOUT, ACK, FLAG3–0, TIMEXP, HBG, REDY,
DMAG1, DMAG2, BR6–1, PA, BRST, CIF, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK,
BMS, TDO, EMU.
@ VDDEXT =Min, IOH=–2.0 mA
2
2 See Output Drive Currents on Page 40 for typical drive current capabilities.
2.4
V
VOL
Low Level Output Voltage
1
@ VDDEXT =Min, IOL=4.0 mA
2
0.4
V
IIH
High Level Input Current
3, 4, 5
3 Applies to input pins:
SBTS, IRQ2–0, HBR, CS, ID2–0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK, CLK_CFG3-0.
4 Applies to input pins with internal pull-ups: DR0, DR1.
5 Applies to input pins with internal pull-ups:
DMARx, TMS, TDI, TRST.
@ VDDEXT =Max, VIN=VDD Max
10
A
IIL
Low Level Input Current
3
@ VDDEXT =Max, VIN=0 V
10
A
IIHC
CLKIN High Level Input Current
6
@ VDDEXT = Max, VIN = VDDEXT Max
25
A
IILC
CLKIN Low Level Input Current
6
@ VDDEXT = Max, VIN = 0 V
25
A
IIKH
Keeper High Load Current
7
@ VDDEXT = Max, VIN = 2.0 V
–250
–50
A
IIKL
Keeper Low Load Current
7
@ VDDEXT = Max, VIN = 0.8 V
50
200
A
IIKH-OD
Keeper High Overdrive Current
7, 8, 9
@ VDDEXT = Max
–300
A
IIKL-OD
Keeper Low Overdrive Current
7, 8, 9
@ VDDEXT = Max
300
A
IILPU1
Low Level Input Current Pull-Up1
4
@ VDDEXT =Max, VIN= 0 V
250
A
IILPU2
Low Level Input Current Pull-Up2
5
@ VDDEXT =Max, VIN= 0 V
500
A
IOZH
Three-State Leakage Current
10, 11, 12, 13
@ VDDEXT=Max, VIN=VDD Max
10
A
IOZL
Three-State Leakage Current
10
@ VDDEXT =Max, VIN=0 V
10
A
IOZHPD
Three-State Leakage Current Pull-Down
13
@ VDDEXT =Max, VIN=VDD Max
250
A
IOZLPU1
Three-State Leakage Current Pull-Up1
11
@ VDDEXT =Max, VIN= 0 V
250
A
IOZLPU2
Three-State Leakage Current Pull-Up2
12
@ VDDEXT =Max, VIN= 0 V
500
A
IOZHA
Three-State Leakage Current
14
@ VDDEXT =Max, VIN=VDD Max
25
A
IOZLA
Three-State Leakage Current
14
@ VDDEXT =Max, VIN=0 V
4
mA
IDD-INPEAK
Supply Current (Internal)
15
tCCLK=10.0 ns, VDDINT=Max
960
mA
IDD-INHIGH
Supply Current (Internal)
16
tCCLK=10.0 ns, VDDINT=Max
715
mA
IDD-INLOW
Supply Current (Internal)
17
tCCLK=10.0 ns, VDDINT=Max
550
mA
IDD-IDLE
Supply Current (Idle)
18
tCCLK=10.0 ns, VDDINT=Max
450
mA
AIDD
Supply Current (Analog)
6
@AVDD=Max
10
mA
CIN
Input Capacitance
19, 20
fIN=1 MHz, TCASE=25°C, VIN=2.5 V
4.7
pF
Specifications subject to change without notice.
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