參數(shù)資料
型號： ADSP-21160NKBZ-100
廠商： Analog Devices Inc
文件頁數(shù)： 34/48頁
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 32BIT 400-BGA
產(chǎn)品培訓模塊： SHARC Processor Overview
標準包裝： 1
系列： SHARC®
類型： 浮點
接口： 主機接口，連接端口，串行端口
時鐘速率： 100MHz
非易失內(nèi)存： 外部
芯片上RAM： 512kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.90V
工作溫度： 0°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 400-BBGA
供應(yīng)商設(shè)備封裝： 400-PBGA（27x27）
包裝： 托盤
ADSP-21160N
–4–
REV. 0
GENERAL DESCRIPTION
The ADSP-21160N SHARC DSP is the second iteration of the
ADSP-21160. Built in a 0.18 micron CMOS process, it offers
higher performance and lower power consumption than its pre-
decessor, the ADSP-21160M. Easing portability, the ADSP-
21160N is application source code compatible with first genera-
tion ADSP-2106x SHARC DSPs in SISD (Single Instruction,
Single Data) mode. To take advantage of the processor’s SIMD
(Single Instruction, Multiple Data) capability, some code
changes are needed. Like other SHARCs, the ADSP-21160N is
a 32-bit processor that is optimized for high performance DSP
applications. The ADSP-21160N includes a 100 MHz core, a
dual-ported on-chip SRAM, an integrated I/O processor with
multiprocessing support, and multiple internal buses to eliminate
I/O bottlenecks.
The ADSP-21160N introduces Single-Instruction,
Multiple-Data (SIMD) processing. Using two computational
units (ADSP-2106x SHARC DSPs have one), the ADSP-
21160N can double performance versus the ADSP-2106x on a
range of DSP algorithms.
Fabricated in a state of the art, high speed, low power CMOS
process, the ADSP-21160N has a 10 ns instruction cycle time.
With its SIMD computational hardware running at 100 MHz,
the ADSP-21160N can perform 600 million math operations per
second.
Table 1 shows performance benchmarks for the ADSP-21160N.
These benchmarks provide single-channel extrapolations of
measured dual-channel processing performance. For more infor-
mation on benchmarking and optimizing DSP code for single-
and dual-channel processing, see the Analog Devices website
The ADSP-21160N continues SHARC’s industry-leading
standards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features. These
features include a 4M-bit dual ported SRAM memory, host
processor interface, I/O processor that supports 14 DMA
channels, two serial ports, six link ports, external parallel bus,
and glueless multiprocessing.
The functional block diagram on Page 1 shows a block diagram
of the ADSP-21160N, illustrating the following architectural
features:
Two processing elements, each made up of an ALU, Mul-
tiplier, Shifter, and Data Register File
Data Address Generators (DAG1, DAG2)
Program sequencer with instruction cache
PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core every core
processor cycle
Interval timer
On-Chip SRAM (4M bits)
External port that supports:
Interfacing to off-chip memory peripherals
Glueless multiprocessing support for six ADSP-
21160N SHARCs
Host port
DMA controller
Serial ports and link ports
JTAG test access port
Figure 1 shows a typical single-processor system. A multiprocess-
ing system appears in Figure 4.
ADSP-21160N Family Core Architecture
The ADSP-21160N includes the following architectural features
of the ADSP-2116x family core. The ADSP-21160N is code
compatible at the assembly level with the ADSP-2106x and
ADSP-21161.
Table 1. ADSP-21160N Benchmarks
Benchmark Algorithm
Speed
1024 Point Complex FFT (Radix 4, with
reversal)
171 s
FIR Filter (per tap)
5 ns
IIR Filter (per biquad)
40 ns
1
1 Specified in SISD mode. Using SIMD, the same benchmark applies for
two sets of computations.For example, two sets of biquad operations can
be performed in the same amount of time as the SISD mode benchmark.
Matrix Multiply (pipelined)
[3 3]
[3 1]
30 ns
[4 4]
[4 1]
37 ns
Divide (y/x)
60 ns
1
Inverse Square Root
90 ns
1
DMA Transfer Rate
800M byte/s
Figure 1. Single-Processor System
3
4
RESET
JTAG
6
ADSP-21160
BMS
CLOCK
LINK
DEVICES
(6 MAX)
(OPTIONAL)
CS
BOOT
EPROM
(OPTIONAL)
ADDR
MEMORY/
MAPPED
DEVICES
(OPTIONAL)
OE
DATA
DMA DEVICE
(OPTIONAL)
DATA
ADDR
DATA
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
CS
RDx
PAGE
CLKOUT
ACK
BR1–6
DMAR1–2
CLKIN
IRQ2–0
LXCLK
TCLK0
RPBA
4
CLK_CFG3–0
EBOOT
LBOOT
FLAG3–0
TIMEXP
LXACK
LXDAT7–0
DR0
DT0
RSF0
TFS0
RCLK0
TCLK1
DR1
DT1
RSF1
TFS1
RCLK1
ID2–0
SERIAL
DEVICE
(OPTIONAL)
SERIAL
DEVICE
(OPTIONAL)
PA
REDY
HBG
HBR
DMAG1–2
SBTS
MS3–0
WRx
DATA63–0
DATA
ADDR
CS
ACK
WE
ADDR31–0
D
A
T
A
C
O
N
T
R
O
L
A
D
R
E
S
CIF
BRST
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參數(shù)描述
ADSP-21161N 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer
ADSP-21161NCCA-100 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
ADSP-21161NCCAZ100 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
ADSP-21161NKCA-100 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
ADSP-21161NKCA-100Z 制造商:Analog Devices 功能描述:
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