參數(shù)資料
型號(hào)： ADSP-21160NKBZ-100
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 4/48頁(yè)
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 32BIT 400-BGA
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： 主機(jī)接口，連接端口，串行端口
時(shí)鐘速率： 100MHz
非易失內(nèi)存： 外部
芯片上RAM： 512kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.90V
工作溫度： 0°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 400-BBGA
供應(yīng)商設(shè)備封裝： 400-PBGA（27x27）
包裝： 托盤
ADSP-21160N
–12–
REV. 0
DMAR2
I/A
DMA Request 2 (DMA Channel 12). Asserted by external port devices to request DMA
services.
DMAR2 has a 20 k
internal pull-up resistor that is enabled on the ADSP-
21160N with ID2–0 = 00x.
ID2–0
I
Multiprocessing ID. Determines which multiprocessing bus request (
BR1–BR6) is used
by ADSP-21160N. ID = 001 corresponds to
BR1, ID = 010 corresponds to BR2, and
so on. Use ID = 000 or ID = 001 in single-processor systems. These lines are a system
configuration selection which should be hardwired or only changed at reset.
DMAG1
O/T
DMA Grant 1 (DMA Channel 11). Asserted by ADSP-21160N to indicate that the
requested DMA starts on the next cycle. Driven by bus master only.
DMAG1 has a
20 k
internal pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x.
DMAG2
O/T
DMA Grant 2 (DMA Channel 12). Asserted by ADSP-21160N to indicate that the
requested DMA starts on the next cycle. Driven by bus master only.
DMAG2 has a
20 k
internal pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x.
BR6–1
I/O/S
Multiprocessing Bus Requests. Used by multiprocessing ADSP-21160Ns to arbitrate
for bus mastership. An ADSP-21160N only drives its own
BRx line (corresponding to
the value of its ID2–0 inputs) and monitors all others. In a multiprocessor system with
less than six ADSP-21160Ns, the unused
BRx pins should be pulled high; the processor’s
own
BRx line must not be pulled high or low because it is an output.
RPBA
I/S
Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for
multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected.
This signal is a system configuration selection which must be set to the same value on
every ADSP-21160N. If the value of RPBA is changed during system operation, it must
be changed in the same CLKIN cycle on every ADSP-21160N.
PA
I/O/T
Priority Access. Asserting its
PA pin allows an ADSP-21160N bus slave to interrupt
background DMA transfers and gain access to the external bus.
PA is connected to all
ADSP-21160Ns in the system. If access priority is not required in a system, the
PA pin
should be left unconnected.
PA has a 20 k
internal pull-up resistor that is enabled on
the ADSP-21160N with ID2–0 = 00x.
DTx
O
Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 k
internal pull-up resistor.
DRx
I
Data Receive (Serial Ports 0, 1). Each DR pin has a 50 k
internal pull-up resistor.
TCLKx
I/O
Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 k
internal pull-up resistor.
RCLKx
I/O
Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 k
internal pull-up resistor.
TFSx
I/O
Transmit Frame Sync (Serial Ports 0, 1).
RFSx
I/O
Receive Frame Sync (Serial Ports 0, 1).
LxDAT7–0
I/O
Link Port Data (Link Ports 0–5). Each LxDAT pin has a 50 k
internal pull-down
resistor that is enabled or disabled by the LPDRD bit of the LCTL0–1 register.
LxCLK
I/O
Link Port Clock (Link Ports 0–5). Each LxCLK pin has a 50 k
internal pull-down
resistor that is enabled or disabled by the LPDRD bit of the LCTL0–1 register.
LxACK
I/O
Link Port Acknowledge (Link Ports 0–5). Each LxACK pin has a 50 k
internal pull-
down resistor that is enabled or disabled by the LPDRD bit of the LCOM register.
EBOOT
I
EPROM Boot Select. For a description of how this pin operates, see Table 3. This signal
is a system configuration selection that should be hardwired.
LBOOT
I
Link Boot. For a description of how this pin operates, see Table 3. This signal is a system
configuration selection that should be hardwired.
BMS
I/O/T
Boot Memory Select. Serves as an output or input as selected with the EBOOT and
LBOOT pins; see Table 3. This input is a system configuration selection that should be
hardwired.
CLKIN
I
Local Clock In. CLKIN is the ADSP-21160N clock input. The ADSP-21160N external
port cycles at the frequency of CLKIN. The instruction cycle rate is a multiple of the
CLKIN frequency; it is programmable at power-up. CLKIN may not be halted,
changed, or operated below the specified frequency.
Table 2. Pin Function Descriptions (continued)
Pin
Type
Function
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ADSP-21161NKCA-100Z 制造商:Analog Devices 功能描述:
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