參數(shù)資料
型號(hào)： ADSP-BF548BBCZ-5A
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 12/100頁(yè)
文件大小： 0K
描述： IC DSP 16BIT 533MHZ 400CSBGA
產(chǎn)品培訓(xùn)模塊： Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
標(biāo)準(zhǔn)包裝： 1
系列： Blackfin®
類(lèi)型： 定點(diǎn)
接口： CAN，SPI，SSP，TWI，UART，USB
時(shí)鐘速率： 533MHz
非易失內(nèi)存： 外部
芯片上RAM： 260kB
電壓 - 輸入/輸出： 2.50V，3.30V
電壓 - 核心： 1.25V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 400-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 400-CSPBGA（17x17）
包裝： 托盤(pán)
配用： ADSP-3PARCBF548M01-ND - MODULE BOARD BF548
ADSP-3PARCBF548E02-ND - KIT DEV STARTER BF548
ADZS-BF548-EZLITE-ND - KIT EZLITE ADZS-BF548
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Rev. C
|
Page 19 of 100
|
February 2010
A third-overtone crystal can be used at frequencies above
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone by adding a tuned inductor circuit as
shown in Figure 7. A design procedure for third-overtone oper-
ation is discussed in detail in an Application Note, Using Third
Overtone Crystals (EE-168).
The Blackfin core runs at a different clock rate than the on-chip
peripherals. As shown in Figure 8 on Page 19, the core clock
(CCLK) and system peripheral clock (SCLK) are derived from
the input clock (CLKIN) signal. An on-chip PLL is capable of
multiplying the CLKIN signal by a programmable 0.5
× to 64×
multiplication factor (bounded by specified minimum and max-
imum VCO frequencies). The default multiplier is 8
×, but it can
be modified by a software instruction sequence. This sequence
is managed by the bfrom_SysControl() function in the on-chip
ROM.
On-the-fly CCLK and SCLK frequency changes can be applied
by using the bfrom_SysControl() function in the on-chip ROM.
Whereas the maximum allowed CCLK and SCLK rates depend
on the applied voltages VDDINT and VDDEXT, the VCO is always
permitted to run up to the frequency specified by the part’s
speed grade.
The CLKOUT pin reflects the SCLK frequency to the off-chip
world. It functions as a reference for many timing specifications.
While inactive by default, it can be enabled using the
EBIU_AMGCTL register.
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 7 illustrates typical system clock ratios. The default
ratio is 4.
Note that the divisor ratio must be chosen to limit the system
clock frequency to its maximum of fSCLK. The SSEL value can be
dynamically changed without any PLL lock latencies by writing
the appropriate values to the PLL divisor register (PLL_DIV)
using the bfrom_SysControl() function in the on-chip ROM.
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 8. The default ratio is 1. This programmable core clock
capability is useful for fast core frequency modifications.
The maximum CCLK frequency not only depends on the part’s
speed grade, it also depends on the applied VDDINT voltage. See
BOOTING MODES
The ADSP-BF54x Blackfin processors have many mechanisms
(listed in Table 9) for automatically loading internal and exter-
nal memory after a reset. The boot mode is specified by four
BMODE input pins dedicated to this purpose. There are two
categories of boot modes: master and slave. In master boot
Figure 7. External Crystal Connections
Note: For CCLK and SCLK specifications, see Table 16.
Figure 8. Frequency Modification Methods
CLKIN
CLKOUT
XTAL
EN
CLKBUF
TO PLL CIRCUITRY
F R OVERTONE
OPERA
O
TION ONLY
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED
DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE
ANALYZE CAREFULLY.
18 pF*
EN
18 pF*
700
0
BLACKFIN
0
*
VDDEXT
1M
PLL
0.5x - 64x
1:15
1, 2, 4, 8
VCO
CLKIN
DYNAMIC MODIFICATION
REQUIRES PLL SEQUENCING
DYNAMIC MODIFICATION
ON-THE-FLY
CCLK
SCLK
Table 7. Example System Clock Ratios
Signal Name
SSEL3–0
Divider Ratio
VCO/SCLK
Example Frequency Ratios
(MHz)
VCO
SCLK
0010
2:1
200
100
0110
6:1
300
50
1010
10:1
500
50
Table 8. Core Clock Ratios
Signal Name
CSEL1–0
Divider Ratio
VCO/CCLK
Example Frequency Ratios
(MHz)
VCO
CCLK
00
1:1
300
01
2:1
300
150
10
4:1
500
125
11
8:1
200
25
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參數(shù)描述
ADSP-BF548BBCZ-5AA 功能描述:IC DSP 16BIT 533MHZ 400CSBGA 制造商:analog devices inc. 系列:Blackfin? 包裝:托盤(pán) 零件狀態(tài):有效 類(lèi)型:定點(diǎn) 接口:CAN，SPI，SSP，TWI，UART，USB 時(shí)鐘速率:533MHz 非易失性存儲(chǔ)器:外部 片載 RAM:260kB 電壓 - I/O:2.50V，3.30V 電壓 - 內(nèi)核:1.25V 工作溫度:-40°C ~ 85°C（TA） 安裝類(lèi)型:表面貼裝 封裝/外殼:400-LFBGA，CSPBGA 供應(yīng)商器件封裝:400-CSPBGA（17x17） 標(biāo)準(zhǔn)包裝:1
ADSP-BF548BBCZ-5X 制造商:Analog Devices 功能描述:- Trays
ADSP-BF548MBBCZ-5M 功能描述:IC DSP 533MHZ W/DDR 400CSPBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類(lèi)型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類(lèi)型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤(pán) 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
ADSP-BF549BBCZ 制造商:Analog Devices 功能描述:
ADSP-BF549BBCZ-ENG 制造商:Analog Devices 功能描述:- Bulk
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