參數(shù)資料
型號(hào): ADSP-BF548BBCZ-5A
廠商: Analog Devices Inc
文件頁數(shù): 75/100頁
文件大?。?/td> 0K
描述: IC DSP 16BIT 533MHZ 400CSBGA
產(chǎn)品培訓(xùn)模塊: Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
標(biāo)準(zhǔn)包裝: 1
系列: Blackfin®
類型: 定點(diǎn)
接口: CAN,SPI,SSP,TWI,UART,USB
時(shí)鐘速率: 533MHz
非易失內(nèi)存: 外部
芯片上RAM: 260kB
電壓 - 輸入/輸出: 2.50V,3.30V
電壓 - 核心: 1.25V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 400-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 400-CSPBGA(17x17)
包裝: 托盤
配用: ADSP-3PARCBF548M01-ND - MODULE BOARD BF548
ADSP-3PARCBF548E02-ND - KIT DEV STARTER BF548
ADZS-BF548-EZLITE-ND - KIT EZLITE ADZS-BF548
Rev. C
|
Page 76 of 100
|
February 2010
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
ATAPI Multiword DMA Transfer Timing
Table 59 and Figure 48 through Figure 51 describe the ATAPI
multiword DMA transfer timing.
Table 59. ATAPI Multiword DMA Transfer Timing
ATAPI Parameter/Description
ATAPI_MULTI_TIM_x Timing Register
Setting1
Timing Equation
t0
Cycle time
TD, TK
(TD + TK)
× t
SCLK
tD
ATAPI_DIOR/ATAPI_DIOW asserted
Pulse Width
TD
× t
SCLK
tF
ATAPI_DIOR data hold
N/A
0
tG(write)
ATAPI_DIOW data setup
TD
× t
SCLK – (tSK1 + tSK2 + tSK4)
tG(read)
ATAPI_DIOR data setup
TD
tOD + tSUD + 2 × tBD + tCDD + tCDC
tH
ATAPI_DIOW data hold
TK
× t
SCLK – (tSK1 + tSK2 + tSK4)
tI
ATAPI_DMACK to
ATAPI_DIOR/ATAPI_DIOW setup
TM
× t
SCLK – (tSK1 + tSK2 + tSK4)
tJ
ATAPI_DIOR/ATAPI_DIOW to
ATAPI_DMACK hold
TK, TEOC_MDMA
(TK + TEOC_MDMA)
× t
SCLK – (tSK1 + tSK2 + tSK4)
tKR
ATAPI_DIOR negated pulse width
TKR
× t
SCLK
tKW
ATAPI_DIOW negated pulse width
TKW
× t
SCLK
tLR
ATAPI_DIOR to ATAPI_DMARQ delay N/A
(TD + TK)
× t
SCLK – (tOD + 2 × tBD + 2 × tCDC)
tM
ATAPI_CS0-1 valid to
ATAPI_DIOR/ATAPI_DIOW
TM
× t
SCLK – (tSK1 + tSK2 + tSK4)
tN
ATAPI_CS0-1 hold
TK, TEOC_MDMA
(TK + TEOC_MDMA)
× t
SCLK – (tSK1 + tSK2 + tSK4)
1 ATAPI timing register setting should be programmed with a value that guarantees parameter compliance with the ATA ANSI specification for an ATA device mode of
operation.
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