參數(shù)資料
型號(hào): ADSP-BF548BBCZ-5A
廠商: Analog Devices Inc
文件頁數(shù): 21/100頁
文件大?。?/td> 0K
描述: IC DSP 16BIT 533MHZ 400CSBGA
產(chǎn)品培訓(xùn)模塊: Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
標(biāo)準(zhǔn)包裝: 1
系列: Blackfin®
類型: 定點(diǎn)
接口: CAN,SPI,SSP,TWI,UART,USB
時(shí)鐘速率: 533MHz
非易失內(nèi)存: 外部
芯片上RAM: 260kB
電壓 - 輸入/輸出: 2.50V,3.30V
電壓 - 核心: 1.25V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 400-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 400-CSPBGA(17x17)
包裝: 托盤
配用: ADSP-3PARCBF548M01-ND - MODULE BOARD BF548
ADSP-3PARCBF548E02-ND - KIT DEV STARTER BF548
ADZS-BF548-EZLITE-ND - KIT EZLITE ADZS-BF548
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Rev. C
|
Page 27 of 100
|
February 2010
Port B: GPIO/TWI1/UART2–3/SPI2 /TMR0–3
PB0/SCL1
I/O GPIO/TWI1 Serial Clock (Open-drain output: requires a pull-up resistor.) E
PB1/SDA1
I/O GPIO/TWI1 Serial Data (Open-drain output: requires a pull-up resistor.) E
PB2/UART3RTS
I/O GPIO/UART3 Request to Send
C
PB3/UART3CTS
I/O GPIO/UART3 Clear to Send
A
PB4/UART2TX
I/O GPIO/UART2 Transmit
A
PB5/UART2RX/TACI2
I/O GPIO/UART2 Receive /Alternate Capture Input 2
A
PB6/UART3TX
I/O GPIO/UART3 Transmit
A
PB7/UART3RX/TACI3
I/O GPIO/UART3 Receive /Alternate Capture Input 3
A
PB8/SPI2SS /TMR0
I/O GPIO/SPI2 Slave Select Input/ Timer 0
A
PB9/SPI2SEL1 /TMR1
I/O GPIO/SPI2 Slave Select Enable 1/ Timer 1
A
PB10 SPI2SEL2/ TMR2
I/O GPIO/SPI2 Slave Select Enable 2/ Timer 2
A
PB11/ SPI2SEL3/ TMR3/ HWAIT
I/O GPIO/SPI2 Slave Select Enable 3/Timer 3/Boot Host Wait
A
PB12/ SPI2SCK
I/O GPIO/SPI2 Clock
A
PB13/ SPI2MOSI
I/O GPIO/SPI2 Master Out Slave In
C
PB14/ SPI2MISO
I/O GPIO/SPI2 Master In Slave Out
C
Port C: GPIO/SPORT0/SD Controller/MXVR (MOST)
PC0 /TFS0
I/O GPIO/SPORT0 Transmit Frame Sync
C
PC1 /DT0SEC/ MMCLK
I/O GPIO/SPORT0 Transmit Data Secondary/MXVR Master Clock
C
PC2 /DT0PRI
I/O GPIO/SPORT0 Transmit Data Primary
C
PC3 /TSCLK0
I/O GPIO/SPORT0 Transmit Serial Clock
A
PC4 /RFS0
I/O GPIO/SPORT0 Receive Frame Sync
C
PC5 /DR0SEC/MBCLK
I/O GPIO/SPORT0 Receive Data Secondary / MXVR Bit Clock
C
PC6 /DR0PRI
I/O GPIO/SPORT0 Receive Data Primary
C
PC7 /RSCLK0
I/O GPIO/SPORT0 Receive Serial Clock
C
PC8 /SD_D0
I/O GPIO/SD Data Bus
A
PC9 /SD_D1
I/O GPIO/SD Data Bus
A
PC10 / SD_D2
I/O GPIO/SD Data Bus
A
PC11 / SD_D3
I/O GPIO/SD Data Bus
A
PC12 / SD_CLK
I/O GPIO/SD Clock Output
A
PC13 / SD_CMD
I/O GPIO/SD Command
A
Table 12. Pin Descriptions (Continued)
Pin Name
I/O1 Function (First / Second/Third/ Fourth)
Driver
Type2
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