參數(shù)資料
型號: ADSP-BF548BBCZ-5A
廠商: Analog Devices Inc
文件頁數(shù): 26/100頁
文件大?。?/td> 0K
描述: IC DSP 16BIT 533MHZ 400CSBGA
產(chǎn)品培訓模塊: Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
標準包裝: 1
系列: Blackfin®
類型: 定點
接口: CAN,SPI,SSP,TWI,UART,USB
時鐘速率: 533MHz
非易失內存: 外部
芯片上RAM: 260kB
電壓 - 輸入/輸出: 2.50V,3.30V
電壓 - 核心: 1.25V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 400-LFBGA,CSPBGA
供應商設備封裝: 400-CSPBGA(17x17)
包裝: 托盤
配用: ADSP-3PARCBF548M01-ND - MODULE BOARD BF548
ADSP-3PARCBF548E02-ND - KIT DEV STARTER BF548
ADZS-BF548-EZLITE-ND - KIT EZLITE ADZS-BF548
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Rev. C
|
Page 31 of 100
|
February 2010
Port J: GPIO/AMC/ATAPI
PJ0 /ARDY/ WAIT
I/O GPIO/ Async Ready/NOR Wait
A
PJ1 /ND_CE7
I/O GPIO/NAND Chip Enable
A
PJ2 /ND_RB
I/O GPIO/NAND Ready Busy
A
PJ3 /ATAPI_DIOR
I/O GPIO/ATAPI Read
A
PJ4 /ATAPI_DIOW
I/O GPIO/ATAPI Write
A
PJ5 /ATAPI_CS0
I/O GPIO/ATAPI Chip Select/Command Block
A
PJ6 /ATAPI_CS1
I/O GPIO/ATAPI Chip Select
A
PJ7 /ATAPI_DMACK
I/O GPIO/ATAPI DMA Acknowledge
A
PJ8 /ATAPI_DMARQ
I/O GPIO/ATAPI DMA Request
A
PJ9 /ATAPI_INTRQ
I/O GPIO/Interrupt Request from the Device
A
PJ10 /ATAPI_IORDY
I/O GPIO/ATAPI Ready Handshake
A
PJ11 /BR
8
I/O GPIO/Bus Request
A
PJ12 /BG
I/O GPIO/Bus Grant
A
PJ13 /BGH6
I/O GPIO/Bus Grant Hang
A
DDR Memory Interface
DA0–12
O
DDR Address Bus
D
DBA0–1
O
DDR Bank Active Strobe
D
DQ0–15
I/O DDR Data Bus
D
DQS0–1
I/O DDR Data Strobe
D
DQM0–1
O
DDR Data Mask for Reads and Writes
D
DCLK0–1
O
DDR Output Clock
D
DCLK0–1
O
DDR Complementary Output Clock
D
DCS0–1
ODDR Chip Selects
D
DCLKE9
O
DDR Clock Enable
D
DRAS
O
DDR Row Address Strobe
D
DCAS
O
DDR Column Address Strobe
D
DWE
ODDR Write Enable
D
DDR_VREF
I
DDR Voltage Reference
DDR_VSSR
I
DDR Voltage Reference Shield (Must be connected to GND.)
Asynchronous Memory Interface
A1-3
O
Address Bus for Async and ATAPI Addresses
A
D0-15/ND_D0-15/ATAPI_D0-15
I/O Data Bus for Async, NAND and ATAPI Accesses
A
AMS0–3
O
Bank Selects (Pull high with a resistor when used as chip select.)
A
ABE0 /ND_CLE
O
Byte Enables : Data Masks for Asynchronous Access/ NAND Command
Latch Enable
A
ABE1/ ND_ALE
O
Byte Enables: Data Masks for Asynchronous Access /NAND Address Latch
Enable
A
AOE /NR_ADV
O
Output Enable /NOR Address Data Valid
A
ARE
ORead Enable / NOR Output Enable
A
AWE
OWrite Enable
A
ATAPI Controller Pins
ATAPI_PDIAG
I
Determines if an 80-pin cable is connected to the host. (Pull high or low
when unused.)
Table 12. Pin Descriptions (Continued)
Pin Name
I/O1 Function (First / Second/Third/ Fourth)
Driver
Type2
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