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參數(shù)資料
型號(hào)： ADSP-BF592KCPZ-2
廠商： Analog Devices Inc
文件頁數(shù)： 22/44頁
文件大?。?/td> 0K
描述： IC DSP CTRLR 200MHZ 64LFCSP
視頻文件： Blackfin? BF592 Introduction
特色產(chǎn)品： Blackfin Embedded Processor
標(biāo)準(zhǔn)包裝： 1
系列： Blackfin®
類型： 定點(diǎn)
接口： I²C，I²S，IrDA，PPI，SPI，SPORT，UART
時(shí)鐘速率： 200MHz
非易失內(nèi)存： ROM（64 kB）
芯片上RAM： 64kB
電壓 - 輸入/輸出： 1.8V，2.5V，3.3V
電壓 - 核心： 1.29V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
Rev. B
|
Page 29 of 44
|
July 2013
Table 24. Serial Ports—External Late Frame Sync
Parameter
VDDEXT
1.8V Nominal
VDDEXT
2.5 V/3.3V Nominal
Min
Max
Min
Max
Unit
Switching Characteristics
tDDTLFSE
Data Delay from Late External TFSx
or External RFSx in multi-channel mode with MFD = 01, 2
12
10
ns
tDTENLFSE
Data Enable from External RFSx in multi-channel mode with
MFD = 01, 2
00ns
1 When in multi-channel mode, TFSx enable and TFSx valid follow tDTENLFSE and tDDTLFSE.
2 If external RFSx/TFSx setup to RSCLKx/TSCLKx > tSCLKE/2 then tDDTTE/I and tDTENE/I apply, otherwise tDDTLFSE and tDTENLFSE apply.
Figure 17. Serial Ports — External Late Frame Sync
RSCLKx
RFSx
DTx
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
EXTERNAL RFSx IN MULTI-CHANNEL MODE
1ST BIT
tDTENLFSE
tDDTLFSE
TSCLKx
TFSx
DTx
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
LATE EXTERNAL TFSx
1ST BIT
tDDTLFSE
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