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| 型號： | ADSP-BF592KCPZ-2 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 40/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CTRLR 200MHZ 64LFCSP |
| 視頻文件： | Blackfin? BF592 Introduction |
| 特色產(chǎn)品： | Blackfin Embedded Processor |
| 標準包裝： | 1 |
| 系列： | Blackfin® |
| 類型： | 定點 |
| 接口： | I²C，I²S，IrDA，PPI，SPI，SPORT，UART |
| 時鐘速率： | 200MHz |
| 非易失內(nèi)存： | ROM（64 kB） |
| 芯片上RAM： | 64kB |
| 電壓 - 輸入/輸出： | 1.8V，2.5V，3.3V |
| 電壓 - 核心： | 1.29V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
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Rev. B
|
Page 5 of 44
|
July 2013
MEMORY ARCHITECTURE
The Blackfin processor views memory as a single unified
4G byte address space, using 32-bit addresses. All resources,
including internal memory and I/O control registers, occupy
separate sections of this common address space. See Figure 3.
The core-accessible L1 memory system is high performance
internal memory that operates at the core clock frequency. The
external bus interface unit (EBIU) provides access to the boot
ROM.
The memory DMA controller provides high bandwidth data-
movement capability. It can perform block transfers of code or
data between the L1 Instruction SRAM and L1 Data SRAM
memory spaces.
Internal (Core-Accessible) Memory
The processor has three blocks of core-accessible memory, pro-
viding high bandwidth access to the core.
The first block is the L1 instruction memory, consisting of
32K bytes SRAM. This memory is accessed at full processor
speed.
The second core-accessible memory block is the L1 data mem-
ory, consisting of 32K bytes. This memory block is accessed at
full processor speed.
The third memory block is a 4K byte L1 scratchpad SRAM,
which runs at the same speed as the other L1 memories.
L1 Utility ROM
The L1 instruction ROM contains utility ROM code. This
includes the TMK (VDK core), C run-time libraries, and DSP
libraries. See the VisualDSP++ documentation for more
information.
Custom ROM (Optional)
The on-chip L1 Instruction ROM on the ADSP-BF592 may be
customized to contain user code with the following features:
64K bytes of L1 Instruction ROM available for custom code
Ability to restrict access to all or specific segments of the
on-chip ROM
Customers wishing to customize the on-chip ROM for their
own application needs should contact ADI sales for more infor-
mation on terms and conditions and details on the technical
implementation.
I/O Memory Space
The processor does not define a separate I/O space. All
resources are mapped through the flat 32-bit address space.
On-chip I/O devices have their control registers mapped into
memory-mapped registers (MMRs) at addresses near the top of
the 4G byte address space. These are separated into two smaller
blocks, one which contains the control MMRs for all core func-
tions, and the other which contains the registers needed for
setup and control of the on-chip peripherals outside of the core.
The MMRs are accessible only in supervisor mode and appear
as reserved space to on-chip peripherals.
Booting from ROM
The processor contains a small on-chip boot kernel, which con-
figures the appropriate peripheral for booting. If the processor is
configured to boot from boot ROM memory space, the proces-
sor starts executing from the on-chip boot ROM. For more
information, see Booting Modes on Page 11.
EVENT HANDLING
The event controller on the processor handles all asynchronous
and synchronous events to the processor. The processor
provides event handling that supports both nesting and prioriti-
zation. Nesting allows multiple event service routines to be
active simultaneously. Prioritization ensures that servicing of a
higher-priority event takes precedence over servicing of a lower-
priority event. The controller provides support for five different
types of events:
Emulation – An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
RESET – This event resets the processor.
Nonmaskable Interrupt (NMI) – The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut-
down of the system.
Figure 3. Internal/External Memory Map
0x0000 0000
0xEF00 0000
0xFF80 0000
0xFF80 8000
0xFFA0 0000
0xFFA0 8000
0xFFA1 0000
0xFFA2 0000
0xFFB0 0000
0xFFB0 1000
0xFFC0 0000
0xFFE0 0000
BOOT ROM (4K BYTES)
RESERVED
L1 INSTRUCTION ROM (64K BYTES)
RESERVED
L1 SCRATCHPAD RAM (4K BYTES)
RESERVED
SYSTEM MEMORY MAPPED REGISTERS (2M BYTES)
CORE MEMORY MAPPED REGISTERS (2M BYTES)
RESERVED
DATA SRAM (32K BYTES)
RESERVED
L1 INSTRUCTION BANK B SRAM (16K BYTES)
RESERVED
0xEF00 1000
0xFFFF FFFF
L1 INSTRUCTION BANK A SRAM (16K BYTES)
0xFFA0 4000
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