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| 型號： | ADSP-BF592KCPZ-2 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 42/44頁 |
| 文件大小： | 0K |
| 描述： | IC DSP CTRLR 200MHZ 64LFCSP |
| 視頻文件： | Blackfin? BF592 Introduction |
| 特色產(chǎn)品： | Blackfin Embedded Processor |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Blackfin® |
| 類型： | 定點 |
| 接口： | I²C，I²S，IrDA，PPI，SPI，SPORT，UART |
| 時鐘速率： | 200MHz |
| 非易失內(nèi)存： | ROM（64 kB） |
| 芯片上RAM： | 64kB |
| 電壓 - 輸入/輸出： | 1.8V，2.5V，3.3V |
| 電壓 - 核心： | 1.29V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
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Rev. B
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Page 7 of 44
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July 2013
initializes the count value of the timer, enables the appropriate
interrupt, then enables the timer. Thereafter, the software must
reload the counter before it counts to zero from the pro-
grammed value. This protects the system from remaining in an
unknown state where software, which would normally reset the
timer, has stopped running due to an external noise condition
or software error.
If configured to generate a hardware reset, the watchdog timer
resets both the core and the processor peripherals. After a reset,
software can determine whether the watchdog was the source of
the hardware reset by interrogating a status bit in the watchdog
timer control register.
The timer is clocked by the system clock (SCLK) at a maximum
frequency of fSCLK.
Timers
There are four general-purpose programmable timer units in
the processor. Three timers have an external pin that can be
configured either as a pulse width modulator (PWM) or timer
output, as an input to clock the timer, or as a mechanism for
measuring pulse widths and periods of external events. These
timers can be synchronized to an external clock input to the sev-
eral other associated PF pins, to an external clock input to the
PPI_CLK input pin, or to the internal SCLK.
The timer units can be used in conjunction with the UART to
measure the width of the pulses in the data stream to provide a
software auto-baud detect function for the respective serial
channels.
The timers can generate interrupts to the processor core provid-
ing periodic events for synchronization, either to the system
clock or to a count of external signals.
In addition to the three general-purpose programmable timers,
a fourth timer is also provided. This extra timer is clocked by the
internal processor clock and is typically used as a system tick
clock for generation of operating system periodic interrupts.
Serial Ports
The ADSP-BF592 processor incorporates two dual-channel
synchronous serial ports (SPORT0 and SPORT1) for serial and
multiprocessor communications. The SPORTs support the fol-
lowing features:
Serial port data can be automatically transferred to and from
on-chip memory/external memory via dedicated DMA chan-
nels. Each of the serial ports can work in conjunction with
another serial port to provide TDM support. In this configura-
tion, one SPORT provides two transmit signals while the other
SPORT provides the two receive signals. The frame sync and
clock are shared.
Serial ports operate in five modes:
Standard DSP serial mode
Multichannel (TDM) mode
I2S mode
Packed I2S mode
Left-justified mode
Serial Peripheral Interface (SPI) Ports
The processor has two SPI-compatible ports that enable the
processor to communicate with multiple SPI-compatible
devices.
The SPI interface uses three pins for transferring data: two data
pins (Master Output-Slave Input, MOSI, and Master Input-
Slave Output, MISO) and a clock pin (serial clock, SCK). An SPI
chip select input pin (SPIx_SS) lets other SPI devices select the
processor, and many SPI chip select output pins (SPIx_SEL7–1)
let the processor select other SPI devices. The SPI select pins are
reconfigured general-purpose I/O pins. Using these pins, the
SPI port provides a full-duplex, synchronous serial interface,
which supports both master/slave modes and multimaster
environments.
UART Port
The ADSP-BF592 processor provides a full-duplex universal
asynchronous receiver/transmitter (UART) port, which is fully
compatible with PC-standard UARTs. The UART port provides
a simplified UART interface to other peripherals or hosts,
supporting full-duplex, DMA-supported, asynchronous trans-
fers of serial data. The UART port includes support for five to
eight data bits, one or two stop bits, and none, even, or odd par-
ity. The UART port supports two modes of operation:
PIO (programmed I/O) – The processor sends or receives
data by writing or reading I/O mapped UART registers.
The data is double-buffered on both transmit and receive.
DMA (direct memory access) – The DMA controller trans-
fers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
Parallel Peripheral Interface (PPI)
The processor provides a parallel peripheral interface (PPI) that
can connect directly to parallel analog-to-digital and digital-to-
analog converters, video encoders and decoders, and other gen-
eral-purpose peripherals. The PPI consists of a dedicated input
clock pin, up to three frame synchronization pins, and up to 16
data pins. The input clock supports parallel data rates up to half
the system clock rate, and the synchronization signals can be
configured as either inputs or outputs.
The PPI supports a variety of general-purpose and ITU-R 656
modes of operation. In general-purpose mode, the PPI provides
half-duplex, bidirectional data transfer with up to 16 bits of
data. Up to three frame synchronization signals are also pro-
vided. In ITU-R 656 mode, the PPI provides half-duplex
bidirectional transfer of 8- or 10-bit video data. Additionally,
on-chip decode of embedded start-of-line (SOL) and start-of-
field (SOF) preamble packets is supported.
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