參數(shù)資料
型號: ADSP-BF592KCPZ-2
廠商: Analog Devices Inc
文件頁數(shù): 29/44頁
文件大?。?/td> 0K
描述: IC DSP CTRLR 200MHZ 64LFCSP
視頻文件: Blackfin? BF592 Introduction
特色產(chǎn)品: Blackfin Embedded Processor
標準包裝: 1
系列: Blackfin®
類型: 定點
接口: I²C,I²S,IrDA,PPI,SPI,SPORT,UART
時鐘速率: 200MHz
非易失內(nèi)存: ROM(64 kB)
芯片上RAM: 64kB
電壓 - 輸入/輸出: 1.8V,2.5V,3.3V
電壓 - 核心: 1.29V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應商設備封裝: 64-LFCSP-VQ(9x9)
包裝: 托盤
Rev. B
|
Page 35 of 44
|
July 2013
JTAG Test And Emulation Port Timing
Table 31 and Figure 24 describe JTAG port operations.
Table 31. JTAG Port Timing
Parameter
VDDEXT
1.8V Nominal
VDDEXT
2.5 V/3.3V Nominal
Min
Max
Min
Max
Unit
Timing Requirements
tTCK
TCK Period
20
ns
tSTAP
TDI, TMS Setup Before TCK High
4
ns
tHTAP
TDI, TMS Hold After TCK High
4
ns
tSSYS
System Inputs Setup Before TCK High1
45ns
tHSYS
System Inputs Hold After TCK High1
55ns
tTRSTW
TRST Pulse Width2 (measured in TCK cycles)
4
TCK
Switching Characteristics
tDTDO
TDO Delay from TCK Low
10
ns
tDSYS
System Outputs Delay After TCK Low
3
13
ns
1 System inputs = SCL, SDA, PF15–0, PG15–0, PH2–0, TCK, NMI, BMODE3–0, PG.
2 50 MHz maximum.
3 System outputs = CLKOUT, SCL, SDA, PF15–0, PG15–0, PH2–0, TDO, EMU, EXT_WAKE.
Figure 24. JTAG Port Timing
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
tTCK
tSTAP
tHTAP
tDTDO
tSSYS
tHSYS
tDSYS
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