- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19509 > ADSP-BF592KCPZ-2 (Analog Devices Inc)IC DSP CTRLR 200MHZ 64LFCSP PDF資料下載
參數(shù)資料
| 型號(hào)： | ADSP-BF592KCPZ-2 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/44頁 |
| 文件大小： | 0K |
| 描述： | IC DSP CTRLR 200MHZ 64LFCSP |
| 視頻文件： | Blackfin? BF592 Introduction |
| 特色產(chǎn)品： | Blackfin Embedded Processor |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Blackfin® |
| 類型： | 定點(diǎn) |
| 接口： | I²C，I²S，IrDA，PPI，SPI，SPORT，UART |
| 時(shí)鐘速率： | 200MHz |
| 非易失內(nèi)存： | ROM（64 kB） |
| 芯片上RAM： | 64kB |
| 電壓 - 輸入/輸出： | 1.8V，2.5V，3.3V |
| 電壓 - 核心： | 1.29V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
第1頁第2頁當(dāng)前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
Rev. B
|
Page 11 of 44
|
July 2013
BOOTING MODES
The processor has several mechanisms (listed in Table 6) for
automatically loading internal and external memory after a
reset. The boot mode is defined by the BMODE input pins dedi-
cated to this purpose. There are two categories of boot modes.
In master boot modes, the processor actively loads data from
parallel or serial memories. In slave boot modes, the processor
receives data from external host devices.
The boot modes listed in Table 6 provide a number of mecha-
nisms for automatically loading the processor’s internal and
external memories after a reset. By default, all boot modes use
the slowest meaningful configuration settings. Default settings
can be altered via the initialization code feature at boot time.
The BMODE pins of the reset configuration register, sampled
during power-on resets and software-initiated resets, imple-
ment the modes shown in Table 6.
IDLE State/No Boot (BMODE - 0x0) — In this mode, the
boot kernel transitions the processor into Idle state. The
processor can then be controlled through JTAG for recov-
ery, debug, or other functions.
SPI1 master boot from flash (BMODE = 0x2) — In this
mode, SPI1 is configured to operate in master mode and to
connect to 8-, 16-, 24-, or 32-bit addressable devices. The
processor uses the PG11/SPI1_SSEL5 to select a single SPI
EEPROM/flash device, submits a read command and suc-
cessive address bytes (0×00) until a valid 8-, 16-, 24-, or 32-
bit addressable device is detected, and begins clocking data
into the processor. Pull-up resistors are required on the
SSEL and MISO pins. By default, a value of 0×85 is written
to the SPI_BAUD register.
SPI1 slave boot from external master (BMODE = 0x3) — In
this mode, SPI1 is configured to operate in slave mode and
to receive the bytes of the .LDR file from a SPI host (mas-
ter) agent. To hold off the host device from transmitting
while the boot ROM is busy, the Blackfin processor asserts
a GPIO pin, called host wait (HWAIT), to signal to the host
device not to send any more bytes until the pin is deas-
serted. The host must interrogate the HWAIT signal,
available on PG4, before transmitting every data unit to the
processor. A pull-up resistor is required on the SPI1_SS
input. A pull-down on the serial clock may improve signal
quality and booting robustness.
SPI0 master boot from flash (BMODE = 0x4) — In this
mode SPI0 is configured to operate in master mode and to
connect to 8-, 16-, 24-, or 32-bit addressable devices. The
processor uses the PF8/SPI0_SSEL2 to select a single SPI
EEPROM/flash device, submits a read command and suc-
cessive address bytes (0×00) until a valid 8-, 16-, 24-, or 32-
bit addressable device is detected, and begins clocking data
into the processor. Pull-up resistors are required on the
SSEL and MISO pins. By default, a value of 0×85 is written
to the SPI_BAUD register.
Boot from PPI host device (BMODE = 0x5) — The proces-
sor operates in PPI slave mode and is configured to receive
the bytes of the LDR file from a PPI host (master) agent.
Boot from UART host device (BMODE = 0x6) — In this
mode UART0 is used as the booting source. Using an auto-
baud handshake sequence, a boot-stream formatted
program is downloaded by the host. The host selects a bit
rate within the UART clocking capabilities. When per-
forming the autobaud, the UART expects a “@” (0×40)
character (eight bits data, one start bit, one stop bit, no par-
ity bit) on the RXD pin to determine the bit rate. The
UART then replies with an acknowledgment which is com-
posed of 4 bytes (0xBF—the value of UART_DLL) and
(0×00—the value of UART_DLH). The host can then
download the boot stream. To hold off the host the proces-
sor signals the host with the boot host wait (HWAIT)
signal. Therefore, the host must monitor the HWAIT, (on
PG4), before every transmitted byte.
Execute from internal L1 ROM (BMODE = 0x7) — In this
mode the processor begins execution from the on-chip 64k
byte L1 instruction ROM starting at address 0xFFA1 0000.
For each of the boot modes (except Execute from internal L1
ROM), a 16 byte header is first brought in from an external
device. The header specifies the number of bytes to be trans-
ferred and the memory destination address. Multiple memory
blocks may be loaded by any boot sequence. Once all blocks are
loaded, program execution commences from the start of L1
instruction SRAM.
The boot kernel differentiates between a regular hardware reset
and a wakeup-from-hibernate event to speed up booting in the
latter case. Bits 7–4 in the system reset configuration (SYSCR)
register can be used to bypass the boot kernel or simulate a
wakeup-from-hibernate boot in case of a software reset.
The boot process can be further customized by “initialization
code.” This is a piece of code that is loaded and executed prior to
the regular application boot. Typically, this is used to speed up
booting by managing the PLL, clock frequencies, or serial bit
rates.
The boot ROM also features C-callable functions that can be
called by the user application at run time. This enables second
stage boot or boot management schemes to be implemented
with ease.
Table 6. Booting Modes
BMODE2– 0 Description
000
Idle/No Boot
001
Reserved
010
SPI1 master boot from Flash, using SPI1_SSEL5 on PG11
011
SPI1 slave boot from external master
100
SPI0 master boot from Flash, using SPI0_SSEL2 on PF8
101
Boot from PPI port
110
Boot from UART host device
111
Execute from Internal L1 ROM
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RBM10DSEH-S13 | CONN EDGECARD 20POS .156 EXTEND |
| NLFV25T-680K-PF | INDUCTOR SHIELD 68UH 10% 252018 |
| XC9536XL-7PCG44C | IC CPLD 36MCELL 7.5NS 44-PLCC |
| TAP685K035SRW | CAP TANT 6.8UF 35V 10% RADIAL |
| VI-B1Y-CY-F1 | CONVERTER MOD DC/DC 3.3V 33W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-BF606BBCZ-4 | 制造商:Analog Devices 功能描述:BLACKFIN DUAL-CORE PROC W/ 128K SRAM - Trays 制造商:Analog Devices 功能描述:IC DSP CTLR DUAL 349CSPBGA 制造商:Analog Devices 功能描述:IC DSC BLACKFIN DUAL 400MH 制造商:Analog Devices 功能描述:IC, DSC, BLACKFIN, DUAL, 400MHZ, BGA-349 制造商:Analog Devices 功能描述:Blackfin Dual-core Proc W/ 128K SRAM 制造商:Analog Devices 功能描述:IC, DSC, BLACKFIN, DUAL, 400MHZ, BGA-349, Series:Blackfin, No. of Bits:32, Frequ 制造商:Analog Devices 功能描述:IC, DSC, BLACKFIN, DUAL, 400MHZ, BGA-349, Series:Blackfin, No. of Bits:32, Frequency:400MHz, Digital IC Case Style:CSPBGA, No. of Pins:349, Core Supply Voltage Min:1.19V, Core Supply Voltage Max:1.32V, Embedded Interface Type:CAN, 制造商:Analog Devices 功能描述:DSP, FLOATING, 32BIT, 400MHZ, CSPBGA-349, Series:Blackfin, No. of Bits:32 bit, Frequency:400MHz, Digital IC Case Style:CSPBGA, No. of Pins:349, Core Supply Voltage Min:1.19V, Core Supply Voltage Max:1.9V, MSL:- , RoHS Compliant: Yes |
| ADSP-BF606KBCZ-4 | 制造商:Analog Devices 功能描述:BLACKFIN DUAL-CORE PROC W/ 128K SRAM - Trays 制造商:Analog Devices 功能描述:Blackfin Dual-core Proc W/ 128K SRAM |
| ADSP-BF607BBCZ-5 | 制造商:Analog Devices 功能描述:DUAL-CORE BLACKFIN PROC W/ 256K L2 SRAM - Trays |
| ADSP-BF607KBCZ-5 | 制造商:Analog Devices 功能描述:DUAL CORE BLACKFIN PROC W/256K L2 SRAM - Trays 制造商:Analog Devices 功能描述:IC DSP CTLR DUAL 349CSPBGA 制造商:Analog Devices 功能描述:IC DSC BLACKFIN DUAL 500MH 制造商:Analog Devices 功能描述:IC, DSC, BLACKFIN, DUAL, 500MHZ, BGA-349 制造商:Analog Devices 功能描述:Dual Core Blackfin Proc w/256K L2 SRAM 制造商:Analog Devices 功能描述:IC, DSC, BLACKFIN, DUAL, 500MHZ, BGA-349, Series:Blackfin, No. of Bits:32, Frequency:400MHz, Digital IC Case Style:CSPBGA, No. of Pins:349, Core Supply Voltage Min:1.19V, Core Supply Voltage Max:1.32V, Embedded Interface Type:CAN, 制造商:Analog Devices 功能描述:DSP, FLOATING, 32BIT, 500MHZ, CSPBGA-349, Series:Blackfin, No. of Bits:32 bit, Frequency:500MHz, Digital IC Case Style:CSPBGA, No. of Pins:349, Core Supply Voltage Min:1.19V, Core Supply Voltage Max:1.9V, MSL:- , RoHS Compliant: Yes |
| ADSP-BF608BBCZ-5 | 制造商:Analog Devices 功能描述:DUAL CORE BLF PROC FOR VGA VIDEO PROC'G - Trays 制造商:Analog Devices 功能描述:IC DSP CTLR DUAL 349CSPBGA 制造商:Analog Devices 功能描述:IC DSC BLACKFIN DUAL 500MH 制造商:Analog Devices 功能描述:IC, DSC, BLACKFIN, DUAL, 500MHZ, BGA-349 制造商:Analog Devices 功能描述:Digital Signal Processors & Controllers - DSP, DSC Blackfin Dual-core VGA Video Proc'g 制造商:Analog Devices 功能描述:IC, DSC, BLACKFIN, DUAL, 500MHZ, BGA-349, Series:Blackfin, No. of Bits:32, Frequ 制造商:Analog Devices 功能描述:Dual Core BlF Proc for VGA Video Procg |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。