參數(shù)資料
型號： ADSP-BF592KCPZ-2
廠商： Analog Devices Inc
文件頁數(shù)： 36/44頁
文件大?。?/td> 0K
描述： IC DSP CTRLR 200MHZ 64LFCSP
視頻文件： Blackfin? BF592 Introduction
特色產品： Blackfin Embedded Processor
標準包裝： 1
系列： Blackfin®
類型： 定點
接口： I²C，I²S，IrDA，PPI，SPI，SPORT，UART
時鐘速率： 200MHz
非易失內存： ROM（64 kB）
芯片上RAM： 64kB
電壓 - 輸入/輸出： 1.8V，2.5V，3.3V
電壓 - 核心： 1.29V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應商設備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
Rev. B
|
Page 41 of 44
|
July 2013
64-LEAD LFCSP LEAD ASSIGNMENT
Table 33 lists the LFCSP leads by signal mnemonic. Table 34
lists the LFCSP by lead number.
Table 33. 64-Lead LFCSP Lead Assignment (Alphabetical by Signal)
Signal
Lead No.
Signal
Lead No.
Signal
Lead No.
Signal
Lead No.
BMODE0
29
PF7
7
PG6
38
TDO
23
BMODE1
28
PF8
10
PG7
39
TMS
21
BMODE2
27
PF9
11
PG8
42
TRST
20
EXTCLK/SCLK
57
PF10
12
PG9
43
VDDEXT
3
CLKIN
61PF11
13PG10
44VDDEXT
14
EMU
19
PF12
15
PG11
45
VDDEXT
25
EXT_WAKE
51
PF13
16
PG12
47
VDDEXT
35
GND
30PF14
17PG13
48VDDEXT
46
NMI
54
PF15
18
PG14
49
VDDEXT
58
PF0
63
PG
52
PG15
50
VDDINT
8
PF1
64
PG0
31
PPI_CLK
56
VDDINT
9
PF2
1
PG1
32
RESET
53
VDDINT
26
PF3
2
PG2
33
SCL
60
VDDINT
40
PF4
4
PG3
34
SDA
59
VDDINT
41
PF5
5
PG4
36
TCK
24
VDDINT
55
PF6
6
PG5
37
TDI
22
XTAL
62
GND
*
65
* Lead no. 65 is the GND supply (see Figure 43 and Figure 44) for the processor (6.2 mm × 6.2 mm); this pad must connect to GND.
Table 34. 64-Lead LFCSP Lead Assignment (Numerical by Lead Number)
Lead No.
Signal
Lead No.
Signal
Lead No.
Signal
Lead No.
Signal
1
PF2
17
PF14
33
PG2
49
PG14
2
PF3
18
PF15
34
PG3
50
PG15
3VDDEXT
19
EMU
35
VDDEXT
51
EXT_WAKE
4PF4
20
TRST
36
PG4
52
PG
5
PF5
21
TMS
37
PG5
53
RESET
6PF6
22
TDI
38
PG6
54
NMI
7PF7
23
TDO
39
PG7
55
VDDINT
8VDDINT
24
TCK
40
VDDINT
56
PPI_CLK
9VDDINT
25
VDDEXT
41
VDDINT
57
EXTCLK/SCLK
10
PF8
26
VDDINT
42
PG8
58
VDDEXT
11
PF9
27BMODE2
43PG9
59
SDA
12
PF10
28
BMODE1
44
PG10
60
SCL
13
PF11
29
BMODE0
45
PG11
61
CLKIN
14
VDDEXT
30
GND
46
VDDEXT
62
XTAL
15
PF12
31
PG0
47
PG12
63
PF0
16
PF13
32
PG1
48
PG13
64
PF1
65
GND*
* Pin no. 65 is the GND supply (see Figure 43 and Figure 44) for the processor (6.2 mm × 6.2 mm); this pad must connect to GND.
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