參數(shù)資料
型號： ADSP-BF592KCPZ-2
廠商： Analog Devices Inc
文件頁數(shù)： 6/44頁
文件大?。?/td> 0K
描述： IC DSP CTRLR 200MHZ 64LFCSP
視頻文件： Blackfin? BF592 Introduction
特色產(chǎn)品： Blackfin Embedded Processor
標(biāo)準(zhǔn)包裝： 1
系列： Blackfin®
類型： 定點(diǎn)
接口： I²C，I²S，IrDA，PPI，SPI，SPORT，UART
時鐘速率： 200MHz
非易失內(nèi)存： ROM（64 kB）
芯片上RAM： 64kB
電壓 - 輸入/輸出： 1.8V，2.5V，3.3V
電壓 - 核心： 1.29V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
Rev. B
|
Page 14 of 44
|
July 2013
SIGNAL DESCRIPTIONS
Signal definitions for the ADSP-BF592 processor are listed in
Table 7. In order to maintain maximum function and reduce
package size and pin count, some pins have dual, multiplexed
functions. In cases where pin function is reconfigurable, the
default state is shown in plain text, while the alternate function
is shown in italics.
During and immediately after reset, all processor signals are
three-stated with the following exceptions: EXT_WAKE is
driven high and XTAL is driven in conjunction with CLKIN to
create a crystal oscillator circuit. During hibernate, all signals
are three-stated with the following exceptions: EXT_WAKE is
driven low and XTAL is driven to a solid logic level.
During and immediately after reset, all I/O pins have their input
buffers disabled with the exception of the pins that need pull-
ups or pull-downs, as noted in Table 7.
Adding a parallel termination to EXTCLK may prove useful in
further enhancing signal integrity. Be sure to verify over-
shoot/undershoot and signal integrity specifications on actual
hardware.
Table 7. Signal Descriptions
Signal Name
Type Function
Driver
Type
Port F: GPIO and Multiplexed Peripherals
PF0–GPIO/DR1SEC/PPI_D8/WAKEN1
I/O GPIO/SPORT1 Receive Data Secondary/PPI Data 8/Wake Enable 1
A
PF1–GPIO/DR1PRI/PPI_D9
I/O GPIO/SPORT1 Receive Data Primary/PPI Data 9
A
PF2–GPIO/RSCLK1/PPI_D10
I/O GPIO/SPORT1 Receive Serial Clock/PPI Data 10
A
PF3–GPIO/RFS1/PPI_D11
I/O GPIO/SPORT1 Receive Frame Sync/PPI Data 11
A
PF4–GPIO/DT1SEC/PPI_D12
I/O GPIO/SPORT1 Transmit Data Secondary/PPI Data 12
A
PF5–GPIO/DT1PRI/PPI_D13
I/O GPIO/SPORT1 Transmit Data Primary/PPI Data 13
A
PF6–GPIO/TSCLK1/PPI_D14
I/O GPIO/SPORT1 Transmit Serial Clock/PPI Data 14
A
PF7–GPIO/TFS1/PPI_D15
I/O GPIO/SPORT1 Transmit Frame Sync/PPI Data 15
A
PF8–GPIO/TMR2/SPI0_SSEL2/WAKEN0
I/O GPIO/Timer 2/SPI0 Slave Select Enable 2/Wake Enable 0
A
PF9–GPIO/TMR0/PPI_FS1/SPI0_SSEL3
I/O GPIO/Timer 0/PPI Frame Sync 1/SPI0 Slave Select Enable 3
A
PF10–GPIO/TMR1/PPI_FS2
I/O GPIO/Timer 1/PPI Frame Sync 2
A
PF11–GPIO/UA_TX/SPI0_SSEL4
I/O GPIO/UART Transmit/SPI0 Slave Select Enable 4
A
PF12–GPIO/UA_RX/SPI0_SSEL7/TACI2–0
I/O GPIO/UART Receive/SPI0 Slave Select Enable 7/Timers 2–0 Alternate Input
Capture
A
PF13–GPIO/SPI0_MOSI/SPI1_SSEL3
I/O GPIO/SPI0 Master Out Slave In/SPI1 Slave Select Enable 3
A
PF14–GPIO/SPI0_MISO/SPI1_SSEL4
I/O GPIO/SPI0 Master In Slave Out/SPI1 Slave Select Enable 4
(This pin should always be pulled high through a 4.7 kΩ resistor,
if booting via the SPI port.)
A
PF15–GPIO/SPI0_SCK/SPI1_SSEL5
I/O GPIO/SPI0 Clock/SPI1 Slave Select Enable 5
A
Port G: GPIO and Multiplexed Peripherals
PG0–GPIO/DR0SEC/SPI0_SSEL1/SPI0_SS
I/O GPIO/SPORT0 Receive Data Secondary/SPI0 Slave Select Enable 1/SPI0 Slave
Select Input
A
PG1–GPIO/DR0PRI/SPI1_SSEL1/WAKEN3
I/O GPIO/SPORT0 Receive Data Primary/SPI1 Slave Select Enable 1/Wake Enable 3
A
PG2–GPIO/RSCLK0/SPI0_SSEL5
I/O GPIO/SPORT0 Receive Serial Clock/SPI0 Slave Select Enable 5
A
PG3–GPIO/RFS0/PPI_FS3
I/O GPIO/SPORT0 Receive Frame Sync/PPI Frame Sync 3
A
PG4–GPIO(HWAIT)/DT0SEC/SPI0_SSEL6
I/O GPIO (HWAIT output for Slave Boot Modes)/SPORT0 Transmit Data
Secondary/SPI0 Slave Select Enable 6
A
PG5–GPIO/DT0PRI/SPI1_SSEL6
I/O GPIO/SPORT0 Transmit Data Primary/SPI1 Slave Select Enable 6
A
PG6–GPIO/TSCLK0
I/O GPIO/SPORT0 Transmit Serial Clock
A
PG7–GPIO/TFS0/SPI1_SSEL7
I/O GPIO/SPORT0 Transmit Frame Sync/SPI1 Slave Select Enable 7
A
PG8–GPIO/SPI1_SCK/PPI_D0
I/O GPIO/SPI1 Clock/PPI Data 0
A
PG9–GPIO/SPI1_MOSI/PPI_D1
I/O GPIO/SPI1 Master Out Slave In/PPI Data 1
A
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