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參數(shù)資料
| 型號(hào)： | AM79C961AKC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP13 |
| 封裝： | CARRIER RING, PLASTIC, QFP-132 |
| 文件頁數(shù)： | 17/85頁 |
| 文件大?。?/td> | 1088K |
| 代理商： | AM79C961AKC |
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Am79C961A
17
P R E L I M I N A R Y
IRQ 3, 4, 5, 9, 10, 11, 12, 15
Interrupt Request
An attention signal which indicates that one or more of
the following status flags is set: BABL, MISS, MERR,
RINT, IDON, RCVCCO, JAB, MPCO, or TXDATSTRT.
All status flags have a mask bit which allows for sup-
pression of IRQ assertion. These flags have the
following meaning:
Output
Because of the operation of the Plug and Play regis-
ters, the interrupts on the PCnet-ISA II must be
attached to specific IRQ signals on the PC/AT bus.
LA17-23
Unlatched Address Bus
The unlatched address bus is driven by the PCnet-ISA
II controller during bus master cycle.
Input/Output
The functions of these unlatched address pins will
change when GPSI mode is invoked. The following
table shows the pin configuration in GPSI mode. Please
refer to the section on General Purpose Serial Interface
for detailed information on accessing this mode.
MASTER
Master Mode
This signal indicates that the PCnet-ISA II controller
has become the Current Master of the ISA bus. After
the PCnet-ISA II controller has received a DMA
Acknowledge (DACK) in response to a DMA Request
Input/Output
(DRQ), the Ethernet controller asserts the MASTER
signal to indicate to the Permanent Master that the
PCnet-ISA II controller is becoming the Current Master.
MEMR
Memory Read
MEMR goes LOW to perform a memory read operation.
MEMW
Memory Write
MEMW goes LOW to perform a memory write
operation.
REF
Memory Refresh
When REF is asserted, a memory refresh is active. The
PCnet-ISA II controller uses this signal to mask inad-
vertent DMA Acknowledge assertion during memory
refresh periods. If DACK is asserted when REF is
active, DACK assertion is ignored. REF is monitored to
eliminate a bus arbitration problem observed on some
ISA platforms.
RESET
Reset
When RESET is asserted HIGH the PCnet-ISA II con-
troller performs an internal system reset. RESET must
be held for a minimum of 10 XTAL1 periods before
being deasserted. While in a reset state, the PCnet-ISA
II controller will tristate or deassert all outputs to pre-
defined reset levels. The PCnet-ISA II controller resets
itself upon power-up.
SA0-19
System Address Bus
This bus contains address information, which is stable
during a bus operation, regardless of the source.
SA17-19 contain the same values as the unlatched
address LA17-19. When the PCnet-ISA II controller is
the Current Master, SA0-19 will be driven actively.
When the PCnet-ISA II controller is not the Current
Master, the SA0-19 lines are continuously monitored to
determine if an address match exists for I/O slave
transfers or Boot PROM accesses.
SBHE
System Byte High Enable
This signal indicates the high byte of the system data
bus is to be used. SBHE is driven by the PCnet-ISA II
controller when performing bus mastering operations.
SD0-15
System Data Bus
These pins are used to transfer data to and from the
PCnet-ISA II controller to system resources via the ISA
data bus. SD0-15 is driven by the PCnet-ISA II control-
Input/Output
Input/Output
Input
Input
Input/Output
Input/Output
Input/Output
BABL
Babble
RCVCCO
Receive Collision Count Overflow
JAB
Jabber
MISS
Missed Frame
MERR
Memory Error
MPCO
Missed Packet Count Overflow
RINT
Receive Interrupt
IDON
Initialization Done
TXDATSTRT
Transmit Start
Pin
Number
Pin Function in Bus
Master Mode
Pin Function in
GPSI Mode
10
LA17
RXDAT
11
LA18
SRDCLK
12
LA19
RXCRS
13
LA20
CLSN
15
LA21
STDCLK
16
LA22
TXEN
17
LA23
TXDAT
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| AM79C961AKC/W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
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| AM79C961AKI/W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C961AKIW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
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