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參數(shù)資料
| 型號： | AM79C961AKC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP13 |
| 封裝： | CARRIER RING, PLASTIC, QFP-132 |
| 文件頁數(shù)： | 68/85頁 |
| 文件大?。?/td> | 1088K |
| 代理商： | AM79C961AKC |
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68
Am79C961A
P R E L I M I N A R Y
When the link test function is enabled (DLNKTST bit in
CSR15 is cleared), the absence of link beat pulses and
receive data on the RXD
±
pair will cause the TMAU to
go into the Link Fail state. In the Link Fail state, data
transmission, data reception, data loopback and the
collision detection functions are disabled and remain
disabled until valid data or greater than 5 consecutive
link pulses appear on the RXD
±
pair. During Link Fail,
the Link Status (LNKST indicated by LED0) signal is
inactive. When the link is identified as functional, the
LNKST signal is asserted, and LED0 output will be
activated. Upon power up or assertion of the RESET
pin, the T-MAU will be forced into the Link Fail state.
Reading the RESET register of the PCnet-ISA
+
(soft-
ware RESET) has no effect on the T-MAU
In order to inter-operate with systems which do not
implement Link Test, this function can be disabled by
setting the DLNKTST bit. With Link Test disabled, the
Data Driver, Receiver and Loopback functions as well
as Collision Detection remain enabled irrespective of
the presence or absence of data or link pulses on the
RXD
±
pair. Link Test pulses continue to be sent regard-
less of the state of the DLNKTST bit.
Polarity Detection and Reversal
The T-MAU receive function includes the ability to
invert the polarity of the signals appearing at the RXD
±
pair if the polarity of the received signal is reversed
(such as in the case of a wiring error). This feature
allows data packets received from a reverse wired
RXD
±
input pair to be corrected in the T-MAU prior to
transfer to the MENDEC. The polarity detection func-
tion is activated following reset or Link Fail, and will
reverse the receive polarity based on both the polarity
of any previous link beat pulses and the polarity of sub-
sequent packets with a valid End Transmit Delimiter
When in the Link Fail state, the T-MAU will recognize
link beat pulses of either positive or negative polarity.
Exit from the Link Fail state occurs at the reception of
5 – 6 consecutive link beat pulses of identical polarity.
On entry to the Link Pass state, the polarity of the last
5 link beat pulses is used to determine the initial
receive polarity configuration and the receiver is
reconfigured to subsequently recognize only link beat
pulses of the previously recognized polarity.
Positive link beat pulses are defined as transmitted sig-
nal with a positive amplitude greater than 585 mV with
a pulse width of 60 ns – 200 ns. This positive excursion
may be followed by a negative excursion. This definition
is consistent with the expected received signal at a cor-
rectly wired receiver, when a link beat pulse, which fits
the template of Figure 14-12 of the 10BASE-T Stan-
dard, is generated at a transmitter and passed through
100 m of twisted pair cable.
Negative link beat pulses are defined as transmitted
signals with a negative amplitude greater than 585 mV
with a pulse width of 60 ns – 200 ns. This negative
excursion may be followed by a positive excursion. This
definition is consistent with the expected received sig-
nal at a reverse wired receiver, when a link beat pulse
which fits the template of Figure 14-12 in the
10BASE-T Standard is generated at a transmitter and
passed through 100 m of twisted pair cable.
The polarity detection/correction algorithm will remain
“armed” until two consecutive packets with valid ETD of
identical polarity are detected. When “armed,” the
receiver is capable of changing the initial or previous
polarity configuration according to the detected ETD
polarity.
On receipt of the first packet with valid ETD following
reset or link fail, the T-MAU will use the inferred polarity
information to configure its RXD
±
input, regardless of
its previous state. On receipt of a second packet with a
valid ETD with correct polarity, the detection/correction
algorithm will “l(fā)ock-in” the received polarity. If the sec-
ond (or subsequent) packet is not detected as confirm-
ing the previous polarity decision, the most recently
detected ETD polarity will be used as the default. Note
that packets with invalid ETD have no effect on updat-
ing the previous polarity decision. Once two consecu-
tive packets with valid ETD have been received, the
T-MAU will lock the correction algorithm until either a
Link Fail condition occurs or RESET is asserted.
During polarity reversal, an internal POL signal will be
active. During normal polarity conditions, this internal
POL signal is inactive. The state of this signal can be
read by software and/or displayed by LED when
enabled by the LED control bits in the ISA Bus Config-
uration Registers (ISACSR5, 6, 7).
Twisted Pair Interface Status
Three internal signals (XMT, RCV and COL) indicate
whether the T-MAU is transmitting, receiving, or in a
collision state. These signals are internal signals and
the behavior of the LED outputs depends on how the
LED output circuitry is programmed.
The T-MAU will power up in the Link Fail state and the
normal algorithm will apply to allow it to enter the Link
Pass state. In the Link Pass state, transmit or receive
activity will be indicated by assertion of RCV signal
going active. If T-MAU is selected using the PORTSEL
bits in CSR15, when moving from AUI to T-MAU selec-
tion, the T-MAU will be forced into the Link Fail state.
In the Link Fail state, XMT, RCV and COL are inactive.
Collision Detect Function
Activity on both twisted pair signals RXD
±
and TXD
±
constitutes a collision, thereby causing the COL signal
to be asserted. (COL is used by the LED control cir-
cuits) COL will remain asserted until one of the two col-
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