參數(shù)資料
型號(hào)： AM79C961AKC
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP13
封裝： CARRIER RING, PLASTIC, QFP-132
文件頁(yè)數(shù)： 81/85頁(yè)
文件大小： 1088K
代理商： AM79C961AKC
Am79C961A
81
P R E L I M I N A R Y
to be inserted. The PCnet-ISA II controller will append
pad bytes dependent on the actual number of bits
transmitted onto the network. Once the last data byte
of the frame has completed prior to appending the
FCS, the PCnet-ISA II controller will check to ensure
that 544 bits have been transmitted. If not, pad bytes
are added to extend the frame size to this value, and
the FCS is then added.
The 544 bit count is derived from the following:
Minimum frame size (excluding preamble,
including FCS)
Preamble/SFD size
FCS size
To be classed as a minimum-size frame at the receiver,
the transmitted frame must contain:
64 bytes
8 bytes
4 bytes
512 bits
64 bits
32 bits
Preamble
+
(Min Frame Size + FCS) bits
At the point that FCS is to be appended, the transmitted
frame should contain:
Preamble
64+
+
(Min Frame Size - FCS) bits
(512-
32) bits
A minimum-length transmit frame from the PCnet-ISA
II controller will, therefore, be 576 bits after the FCS is
appended.
Transmit FCS Generation
Automatic generation and transmission of FCS for a
transmit frame depends on the value of DXMTFCS bit
in CSR15. When DXMTFCS = 0 the transmitter will
generate and append the FCS to the transmitted frame.
If the automatic padding feature is invoked
(APAD_XMT is SET in CSR4), the FCS will be
appended by the PCnet-ISA II controller regardless of
the state of DXMTFCS. Note that the calculated FCS is
transmitted most-significant bit first. The default value
of DXMTFCS is 0 after RESET.
Transmit Exception Conditions
Exception conditions for frame transmission fall into
two distinct categories; those which are the result of
normal network operation, and those which occur due
to abnormal network and/or host related events.
Normal events which may occur and which are handled
autonomously by the PCnet-ISA II controller are basi-
cally collisions within the slot time with automatic retry.
The PCnet-ISA II controller will ensure that collisions
which occur within 512 bit times from the start of trans-
mission (including preamble) will be automatically
retried with no host intervention. The transmit FIFO en-
sures this by guaranteeing that data contained within
the FIFO will not be overwritten until at least 64 bytes
(512 bits) of data have been successfully transmitted
onto the network.
If 16 total attempts (initial attempt plus 15 retries) fail,
the PCnet-ISA II controller sets the RTRY bit in the cur-
rent transmit TDTE in host memory (TMD2), gives up
ownership (sets the OWN bit to zero) for this packet,
and processes the next packet in the transmit ring for
transmission.
ISO 8802-3 (IEEE/ANSI 802.3) Data Frame
Preamble
1010....1010
SYNC
10101011
Dest.
ADDR
SRCE.
ADDR.
Length
LLC
Data
Pad
FCS
56
Bits
8
Bits
6
Bytes
6
Bytes
2
Bytes
46-1500
Bytes
4
Bytes
19364A-16
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AM79C961AKI/W 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller
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