參數(shù)資料
型號(hào)： AM79C961AKC
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP13
封裝： CARRIER RING, PLASTIC, QFP-132
文件頁(yè)數(shù)： 83/85頁(yè)
文件大?。?/td> 1088K
代理商： AM79C961AKC
Am79C961A
83
P R E L I M I N A R Y
IEEE/ANSI 802.3 Frame and Length Field Transmission Order
Receive FCS Checking
Reception and checking of the received FCS is per-
formed automatically by the PCnet-ISA II controller.
Note that if the Automatic Pad Stripping feature is
enabled, the received FCS will be verified against the
value computed for the incoming bit stream including
pad characters, but it will not be passed to the host. If
a FCS error is detected, this will be reported by the
CRC bit in RMD1.
Receive Exception Conditions
Exception conditions for frame reception fall into two
distinct categories; those which are the result of normal
network operation, and those which occur due to
abnormal network and/or host related events.
Normal events which may occur and which are handled
autonomously by the PCnet-ISA II controller are basi-
cally collisions within the slot time and automatic runt
packet rejection. The PCnet-ISA II controller will ensure
that collisions which occur within 512 bit times from the
start of reception (excluding preamble) will be automat-
ically deleted from the receive FIFO with no host inter-
vention. The receive FIFO will delete any frame which
is composed of fewer than 64 bytes provided that the
Runt Packet Accept (RPA bit in CSR124) feature has
not been enabled. This criteria will be met regardless of
whether the receive frame was the first (or only) frame
in the FIFO or if the receive frame was queued behind
a previously received message.
Abnormal network conditions include:
I
FCS errors
I
Late collision
These should not occur on a correctly configured 802.3
network and will be reported if they do.
Host related receive exception conditions include
MISS, BUFF, and OFLO. These are described in the
Receive Descriptor section.
Preamble
1010....1010
SYNCH
10101011
Dest.
ADDR.
Srce.
ADDR.
Length
LLC
DATA
Pad
FCS
56
Bits
8
Bits
6
Bytes
6
Bytes
2
Bytes
46–1500
Bytes
4
Bytes
Most
Significant
Byte
Least
Significant
Byte
Bit
0
Bit
7
Start of Packet
at Time= 0
Increasing Time
Bit
7
Bit
0
45–0
Bytes
1–1500
Bytes
19364A-17
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