參數(shù)資料
型號(hào)： AM79C961AKC
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP13
封裝： CARRIER RING, PLASTIC, QFP-132
文件頁(yè)數(shù)： 72/85頁(yè)
文件大小： 1088K
代理商： AM79C961AKC
72
Am79C961A
P R E L I M I N A R Y
IEEE 1149.1 Test Access Port Interface
An IEEE 1149.1 compatible boundary scan Test Access
Port is provided for board-level continuity test and diag-
nostics. All digital input, output, and input/output pins are
tested. Analog pins, including the AUI differential driver
(DO
±
) and receivers (DI
±
, CI
±
), and the crystal input
(XTAL1/XTAL2) pins, are tested. The T-MAU drivers
TXD
±
, TXP
±
, and receiver RXD
±
are also tested.
The following is a brief summary of the IEEE 1149.1
compatible test functions implemented in the
PCnet-ISA II
controller.
Boundary Scan Circuit
The boundary scan test circuit requires four extra pins
(TCK, TMS, TDI and TDO), defined as the Test Access
Port (TAP). It includes a finite state machine (FSM), an
instruction register, a data register array, and a
power-on reset circuit. Internal pull-up resistors are
provided for the TDI, TCK, and TMS pins. The TCK pin
must not be left unconnected. The boundary scan cir-
cuit remains active during sleep.
TAP FSM
The TAP engine is a 16-state FSM, driven by the Test
Clock (TCK) and the Test Mode Select (TMS) pins. This
FSM is in its reset state at power-up or RESET. An
independent power-on reset circuit is provided to
ensure the FSM is in the TEST_LOGIC_RESET state
at power-up.
Supported Instructions
In addition to the minimum IEEE 1149.1 requirements
(BYPASS, EXTEST and SAMPLE instructions), three
additional instructions (IDCODE, TRIBYP and SETBYP)
are provided to further ease board-level testing. All
unused instruction codes are reserved. See the table
below for a summary of supported instructions.
Instruction Register and Decoding Logic
After hardware or software RESET, the IDCODE
instruction is always invoked. The decoding logic gives
signals to control the data flow in the DATA registers
according to the current instruction.
Boundary Scan Register (BSR)
Each BSR cell has two stages. A flip-flop and a latch
are used in the SERIAL SHIFT STAGE and the PARAL-
LEL OUTPUT STAGE, respectively.
There are four possible operational modes in the BSR cell:
Other Data Registers
(1) BYPASS REG (1 BIT)
(2) DEV ID REG (32 bits
IEEE 1149.1 Supported Instruction Summary
Power Saving Modes
The PCnet-ISA II controller supports two hardware
power-savings modes. Both are entered by asserting
the SLEEP pin LOW.
In
coma
mode, the PCnet-ISA II controller will go into
deep sleep with no support to automatically wake itself
up. Sleep mode is enabled when the AWAKE bit in
ISACSR2 is reset. This mode is the default powerdown
mode.
In
Snooze
mode, enabled by setting the AWAKE bit in
ISACSR2 and driving the SLEEP pin LOW, the T-MAU
receive circuitry will remain enabled even while the
SLEEP pin is driven LOW. The LED0 output will also
continue to function, indicating a good 10BASE-T link if
1
2
3
4
Capture
Shift
Update
System Function
Bits 31–28:
Bits 27–12:
Bits 11–1:
Version
Part number
(2261h)
Manufacturer ID. The 11 bit
manufacturer ID code for AMD is
00000000001 according to JEDEC
Publication 106-A.
Always a logic 1
Bit 0:
Instruction
Name
Description
Selected
Data Reg
Mode
Instruction
Code
EXTEST
External Test
BSR
Test
0000
IDCODE
ID Code Inspection
ID REG
Normal
0001
SAMPLE
Sample Boundary
BSR
Normal
0010
TRIBYP
Force Tristate
Bypass
Normal
0011
SETBYP
Control Boundary to 1/0
Bypass
Test
0100
BYPASS
Bypass Scan
Bypass
Normal
1111
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