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參數(shù)資料
| 型號： | AM79C972BVCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| 中文描述： | 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁數(shù)： | 107/130頁 |
| 文件大?。?/td> | 1580K |
| 代理商： | AM79C972BVCW |
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Am79C972
107
When MERR is set, INTA is as-
serted if IENA is 1 and the mask
bit MERRM (CSR3, bit 11) is 0.
MERR assertion will set the ERR
bit, regardless of the settings of
IENA and MERRM.
Read/Write accessible always.
MERR is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
MERR
is
H_RESET, S_RESET, or by set-
ting the STOP bit.
cleared
by
10
RINT
Receive Interrupt is set by the
Am79C972 controller after the
last descriptor of a receive frame
has been updated by writing a 0
to the OWNership bit. RINT may
also be set when the first descrip-
tor of a receive frame has been
updated by writing a 0 to the
OWNership bit if the LAPPEN bit
of CSR3 has been set to a 1.
When RINT is set, INTA is assert-
ed if IENA is 1 and the mask bit
RINTM (CSR3, bit 10) is 0.
Read/Write accessible always.
RINT is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
RINT
is
H_RESET, S_RESET, or by set-
ting the STOP bit.
cleared
by
9
TINT
Transmit Interrupt is set by the
Am79C972 controller after the
OWN bit in the last descriptor of a
transmit frame has been cleared
to indicate the frame has been
sent or an error occurred in the
transmission.
When TINT is set, INTA is assert-
ed if IENA is 1 and the mask bit
TINTM (CSR3, bit 9) is 0.
TINT will not be set if TINTOKD
(CSR5, bit 15) is set to 1 and the
transmission was successful.
Read/Write accessible always.
TINT is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
TINT
is
H_RESET, S_RESET, or by set-
ting the STOP bit.
cleared
by
8
IDON
Initialization Done is set by the
Am79C972 controller after the
initialization sequence has com-
pleted. When IDON is set, the
Am79C972 controller has read
the initialization block from mem-
ory.
When IDON is set, INTA is as-
serted if IENA is 1 and the mask
bit IDONM (CSR3, bit 8) is 0.
Read/Write accessible always.
IDON is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
IDON
is
H_RESET, S_RESET, or by set-
ting the STOP bit.
cleared
by
7
INTR
Interrupt Flag indicates that one
or more following interrupt caus-
ing conditions has occurred:
EXDINT, IDON, MERR, MISS,
MFCO, RCVCCO, RINT, SINT,
TINT, TXSTRT, UINT, STINT,
MREINT, MCCINT, MIIPDTINT,
MAPINT and the associated
mask or enable bit is pro-
grammed to allow the event to
cause an interrupt. If IENA is set
to 1 and INTR is set, INTA will be
active. When INTR is set by SINT
or SLPINT, INTA will be active in-
dependent of the state of IENA.
Read accessible always. INTR is
read only. INTR is cleared by
clearing all of the active individual
interrupt bits that have not been
masked out.
6
IENA
Interrupt Enable allows INTA to
be active if the Interrupt Flag is
set. If IENA = 0, then INTA will be
disabled regardless of the state
of INTR.
Read/Write accessible always.
IENA is set by writing a 1 and
cleared by writing a 0. IENA is
cleared
by
S_RESET and setting the STOP
bit.
H_RESET
or
5
RXON
Receive On indicates that the re-
ceive function is enabled. RXON
is set if DRX (CSR15, bit 0) is set
to 0 after the START bit is set. If
INIT and START are set together,
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