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參數(shù)資料
| 型號： | AM79C972BVCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| 中文描述： | 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁數(shù)： | 116/130頁 |
| 文件大小： | 1580K |
| 代理商： | AM79C972BVCW |
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116
Am79C972
by H_RESET, S_RESET, or
STOP.
11-8
RLEN
Contains a copy of the receive
encoded ring length (RLEN) read
from the initialization block during
Am79C972 controller initializa-
tion. This field is written during
the Am79C972 controller initial-
ization routine.
Read accessible only when either
the STOP or the SPND bit is set.
Write operations have no effect
and should not be performed.
RLEN is only defined after initial-
ization. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
7-0
RES
Reserved locations. Read as 0s.
Write operations are ignored.
CSR7: Extended Control and Interrupt 2
Certain bits in CSR7 indicate the cause of an interrupt.
The register is designed so that these indicator bits are
cleared by writing ones to those bit locations. This
means that the software can read CSR7 and write back
the value just read to clear the interrupt condition.
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15
FASTSPNDE
Fast Suspend Enable. When
FASTSPNDE is set to 1, the
Am79C972 controller performs a
fast suspend
SPND bit is set.
whenever the
When a fast suspend is request-
ed, the Am79C972 controller per-
forms a quick entry into the
suspend mode. At the time the
SPND bit is set, the Am79C972
controller will complete the DMA
process of any transmit and/or re-
ceive packet that had already be-
gun DMA activity. In addition, any
transmit packet that had started
transmission will be fully transmit-
ted and any receive packet that
had begun reception will be fully
received. However, no additional
packets will be transmitted or re-
ceived and no additional transmit
or receive DMA activity will begin.
Hence, the Am79C972 controller
may enter the suspend mode
with transmit and/or receive
packets still in the FIFOs or the
SRAM.
When FASTSPNDE is 0 and the
SPND bit is set, the Am79C972
controller may take longer before
entering the suspend mode. At
the time the SPND bit is set, the
Am79C972 controller will com-
plete the DMA process of a trans-
mit packet if it had already begun
and the Am79C972 controller will
completely receive a receive
packet if it had already begun.
Additionally, all transmit packets
stored in the transmit FIFOs and
the transmit buffer area in the
SRAM (if one is enabled) will be
transmitted and all receive pack-
ets stored in the receive FIFOs,
and the receive buffer area in the
SRAM (if one is enabled) will be
transferred into system memory.
Since the FIFO and SRAM con-
tents are flushed, it may take
much
longer
Am79C972 controller enters the
suspend mode. The amount of
time that it takes depends on
many factors including the size of
the SRAM, bus latency, and net-
work traffic level.
before
the
When a write to CSR5 is per-
formed with bit 0 (SPND) set to 1,
the value that is simultaneously
written to FASTSPNDE is used to
determine which approach is
used to enter suspend mode.
Read/Write accessible always.
FASTSPNDE
is
H_RESET, S_RESET or by set-
ting the STOP bit.
cleared
by
14
RXFRTG
Receive Frame Tag. When Re-
ceive Frame Tag is set to 1, a tag
word is put into the receive de-
scriptor supplied by the EADI.
See the section
Receive Frame
Tagging
for details. This bit is
valid only when the EADISEL
(BCR2, bit 3) is set to 1.
Read/Write accessible always.
RXFRTG
is
H_RESET. RXFRTG is unaffect-
cleared
by
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