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參數(shù)資料
| 型號： | AM79C972BVCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| 中文描述： | 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁數(shù)： | 98/130頁 |
| 文件大?。?/td> | 1580K |
| 代理商： | AM79C972BVCW |
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98
Am79C972
valid memory address before set-
ting MEMEN. The Am79C972
controller will only respond to ac-
cesses to the Expansion ROM
when both ROMEN (PCI Expan-
sion ROM Base Address register,
bit 0) and MEMEN are set to 1.
Since MEMEN also enables the
memory mapped access to the
Am79C972 I/O resources, the
PCI Memory Mapped I/O Base
Address register must be pro-
grammed with an address so that
the device does not claim cycles
not intended for it.
MEMEN is cleared by H_RESET
and is not effected by S_RESET
or by setting the STOP bit.
0
IOEN
I/O Space Access Enable. The
Am79C972 controller will ignore
all I/O accesses when IOEN is
cleared. The host must set IOEN
before the first I/O access to the
device. The PCI I/O Base Ad-
dress register must be pro-
grammed with a valid I/O address
before setting IOEN.
IOEN is cleared by H_RESET
and is not effected by S_RESET
or by setting the STOP bit.
PCI Status Register
Offset 06h
The PCI Status register is a 16-bit register that contains
status information for the PCI bus related events. It is
located at offset 06h in the PCI Configuration Space.
Bit
Name
Description
15
PERR
Parity Error. PERR is set when
the Am79C972 controller detects
a parity error.
The Am79C972 controller sam-
ples the AD[31:0], C/BE[3:0], and
the PAR lines for a parity error at
the following times:
In slave mode, during the ad-
dress phase of any PCI bus com-
mand.
In slave mode, for all I/O, mem-
ory and configuration write com-
mands that select the Am79C972
controller when data is trans-
ferred (TRDY and IRDY are as-
serted).
In master mode, during the data
phase of all memory read com-
mands.
In master mode, during the data
phase of the memory write com-
mand, the Am79C972 controller
sets the PERR bit if the target re-
ports a data parity error by as-
serting the PERR signal.
PERR is not effected by the state
of the Parity Error Response en-
able bit (PCI Command register,
bit 6).
PERR is set by the Am79C972
controller and cleared by writing a
1. Writing a 0 has no effect.
PERR is cleared by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
14
SERR
Signaled SERR. SERR is set
when the Am79C972 controller
detects an address parity error
and both SERREN and PERREN
(PCI Command register, bits 8
and 6) are set.
SERR is set by the Am79C972
controller and cleared by writing a
1. Writing a 0 has no effect.
SERR is cleared by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
13
RMABORT Received Master Abort. RM-
ABORT
Am79C972 controller terminates
a master cycle with a master
abort sequence.
is
set
when
the
RMABORT
Am79C972
cleared by writing a 1. Writing a 0
has no effect. RMABORT is
cleared by H_RESET and is not
affected by S_RESET or by set-
ting the STOP bit.
is
set
by
the
and
controller
12
RTABORT
Received Target Abort. RT-
ABORT is set when a target ter-
minates an Am79C972 master
cycle with a target abort se-
quence.
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