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參數(shù)資料
| 型號： | AM79C972BVCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| 中文描述： | 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁數(shù)： | 24/130頁 |
| 文件大?。?/td> | 1580K |
| 代理商： | AM79C972BVCW |
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24
Am79C972
SRD
Serial Receive Data
SRD is the decoded NRZ data from the network when
in GPSI mode. This signal can be used for external ad-
dress detection.
Input/Output
Note:
When the MII port is selected, SRD will not gen-
erate transitions and receive data must be derived from
the Media Independent Interface RXD[3:0] pins.
Note also that the SRD pin is multiplexed with the
MIIRXFRTGD, EEDO, and LED3 pins
.
SRDCLK
Serial Receive Data Clock
Serial Receive Data is synchronous with reference to
SRDCLK.
Output
Note:
When the MII port is selected, SRDCLK will not
generate transitions and the receive clock must be de-
rived from the MII RX_CLK pin.
Note also that the SRDCLK pin is multiplexed with the
MIIRXFRTGE and LED2 pins
.
RXFRTGD
Receive Frame Tag Data
When the EADI is enabled (EADISEL, BCR2, bit 3), the
Receive Frame Tagging is enabled (RXFRTG, CSR7,
bit 14), and the MII is not selected, the RXFRTGD pin
becomes a data input pin for the Receive Frame Tag.
See the
Receive Frame Tagging
section for details.
Input
Note:
The RXFRTGD pin is multiplexed with the
RXD[0] pin.
RXFRTGE
Receive Frame Tag Enable
When the EADI is enabled (EADISEL, BCR2, bit 3), the
Receive Frame Tagging is enabled (RXFRTG, CSR7,
bit 14), and the MII is not selected, the RXFRTGE pin
becomes a data input enable pin for the Receive Frame
Tag. See the
Receive Frame Tagging
section for de-
tails.
Input
Note:
The RXFRTGE pin is multiplexed with the
RX_DV pin.
MIIRXFRTGD
MII Receive Frame Tag Enable
When the EADI is enabled (EADISEL, BCR2, bit 3), the
Receive Frame Tagging is enabled (RXFRTG, CSR7,
bit 14), and the MII is selected, the MIIRXFRTGD pin
becomes a data input pin for the Receive Frame Tag.
See the
Receive Frame Tagging
section for details.
Input
Note:
The MIIRXFRTGD pin is multiplexed with the
SRD, EEDO, and LED3 pins.
MIIRXFRTGE
MII Receive Frame Tag Enable
When the EADI is enabled (EADISEL, BCR2, bit 3), the
Receive Frame Tagging is enabled (RXFRTG, CSR7,
bit 14), and the MII is selected, the MIIRXFRTGE pin
becomes a data input enable pin for the Receive Frame
Tag. See the
Receive Frame Tagging
section for de-
tails.
Input
Note:
The MIIRXFRTGE pin is multiplexed with the
SRDCLK and LED2 pins.
IEEE 1149.1 (1990) Test Access Port
Interface
TCK
Test Clock
TCK is the clock input for the boundary scan test mode
operation. It can operate at a frequency of up to 10
MHz. TCK has an internal pull up resistor.
TDI
Test Data In
TDI is the test data input path to the Am79C972 con-
troller. The pin has an internal pull up resistor.
TDO
Test Data Out
TDO is the test data output path from the Am79C972
controller. The pin is tri-stated when the JTAG port is in-
active.
TMS
Test Mode Select
A serial input bit stream on the TMS pin is used to de-
fine the specific boundary scan test to be executed.
The pin has an internal pull up resistor.
Input
Input
Output
Input
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相關代理商/技術參數(shù) |
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|---|---|
| AM79C972BVD\\W | 制造商:Advanced Micro Devices 功能描述: |
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| AM79C973 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973/75 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Board Layout Considerations for the Am79C973/75 Network Interface? - (PDF) |
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