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| 型號(hào)： | AM79C972BVCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| 中文描述： | 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁(yè)數(shù)： | 47/130頁(yè) |
| 文件大?。?/td> | 1580K |
| 代理商： | AM79C972BVCW |
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Am79C972
47
Table 5.
Descriptor Write Sequence
FIFO DMA Transfers
Am79C972 microcode will determine when a FIFO
DMA transfer is required. This transfer mode will be
used for transfers of data to and from the Am79C972
FIFOs. Once the Am79C972 BIU has been granted bus
mastership, it will perform a series of consecutive
transfer cycles before relinquishing the bus. All trans-
fers within the master cycle will be either read or write
cycles, and all transfers will be to contiguous, ascend-
ing addresses. Both non-burst and burst cycles are
used, with burst mode being the preferred mode when
the device is used in a PCI bus application.
Non-Burst FIFO DMA Transfers
In the default mode, the Am79C972 controller uses
non-burst transfers to read and write data when ac-
cessing the FIFOs. Each non-burst transfer will be per-
formed sequentially with the issue of an address and
the transfer of the corresponding data with appropriate
output signals to indicate selection of the active data
bytes during the transfer.
FRAME will be deasserted after every address phase.
Several factors will affect the length of the bus master-
ship period. The possibilities are as follows:
Bus cycles will continue until the transmit FIFO is filled
to its high threshold (read transfers) or the receive FIFO
is emptied to its low threshold (write transfers). The
exact number of total transfer cycles in the bus master-
ship period is dependent on all of the following vari-
ables: the settings of the FIFO watermarks, the
conditions of the FIFOs, the latency of the system bus
to the Am79C972 controller
’
s bus request, the speed of
bus operation and bus preemption events. The TRDY
response time of the memory device will also affect the
number of transfers, since the speed of the accesses
will affect the state of the FIFO. During accesses, the
FIFO may be filling or emptying on the network end. For
example, on a receive operation, a slower TRDY re-
sponse will allow additional data to accumulate inside
of the FIFO. If the accesses are slow enough, a com-
plete DWord may become available before the end of
the bus mastership period and, thereby, increase the
number of transfers in that period. The general rule is
that the longer the Bus Grant latency, the slower the
bus transfer operations; the slower the clock speed, the
higher the transmit watermark; or the higher the re-
ceive watermark, the longer the bus mastership period
will be.
Note:
The PCI Latency Timer is not significant during
non-burst transfers.
SWSTYLE
BCR20[7:0]
BWRITE
BCR18[5]
AD Bus Sequence
Address = XXXX XX04h
Data = MD2[15:0],
MD1[15:0]
Idle
Address = XXXX XX00h
Data = MD1[31:24]
Address = XXXX XX08h
Data = MD2[31:0]
Idle
Address = XXXX XX04h
Data = MD1[31:16]
Address = XXXX XX00h
Data = MD2[31:0]
Idle
Address = XXXX XX04h
Data = MD1[31:16]
Address = XXXX XX00h
Data = MD2[31:0]
Data = MD1[31:16]
0
X
2
X
3
0
3
1
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相關(guān)代理商/技術(shù)參數(shù) |
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| AM79C972BVD\\W | 制造商:Advanced Micro Devices 功能描述: |
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