參數(shù)資料
型號(hào)： AM79C978AVCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： Single-Chip 1/10 Mbps PCI Home Networking Controller
中文描述： 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： TQFP-144
文件頁(yè)數(shù)： 100/256頁(yè)
文件大?。?/td> 3505K
代理商： AM79C978AVCW
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100
Am79C978A
The PCI Device ID register is located at offset 02h in
the PCI Configuration Space. It is read only.
PCI Command Register
Offset 04h
The PCI Command register is a 16-bit register used to
control the gross functionality of the Am79C978A con-
troller. It controls the Am79C978A controller
’
s ability to
generate and respond to PCI bus cycles. To logically
disconnect the Am79C978A device from all PCI bus
cycles except configuration cycles, a value of 0 should
be written to this register.
The PCI Command register is located at offset 04h in
the PCI Configuration Space. It is read and written by
the host.
Bit
Name
Description
15-10
RES
Reserved locations. Read as ze-
ros; write operations have no
effect.
9
FBTBEN
Fast Back-to-Back Enable. Read
as zero; write operations have no
effect. The Am79C978A control-
ler
will
not
Back-to-Back cycles.
generate
Fast
8
SERREN
SERR Enable. Controls the as-
sertion of the SERR pin. SERR is
disabled
when
cleared. SERR will be asserted
on detection of an address parity
error and if both SERREN and
PERREN (bit 6 of this register)
are set.
SERREN
is
SERREN
H_RESET and is not effected by
S_RESET or by setting the STOP
bit.
is
cleared
by
7
RES
Reserved location. Read as ze-
ros; write operations have no
effect.
6
PERREN
Parity Error Response Enable.
Enables the parity error response
functions. When PERREN is 0
and the Am79C978A controller
detects a parity error, it only sets
the Detected Parity Error bit in
the PCI Status register. When
PERREN is 1, the Am79C978A
controller asserts PERR on the
detection of a data parity error. It
also sets the DATAPERR bit (PCI
Status register, bit 8), when the
data parity error occurred during
a master cycle. PERREN also
enables reporting address parity
errors through the SERR pin and
the SERR bit in the PCI Status
register.
PERREN
H_RESET and is not affected by
S_RESET or by setting the STOP
bit.
is
cleared
by
5
VGASNOOP
VGA Palette Snoop. Read as ze-
ro; write operations have no
effect.
4
MWIEN
Memory Write and Invalidate Cy-
cle Enable. Read as zero; write
operations have no effect. The
Am79C978A controller only gen-
erates Memory Write cycles.
3
SCYCEN
Special Cycle Enable. Read as
zero; write operations have no ef-
fect. The Am79C978A controller
ignores all Special Cycle opera-
tions.
2
BMEN
Bus Master Enable. Setting
BMEN enables the Am79C978A
controller to become a bus mas-
ter on the PCI bus. The host must
set BMEN before setting the INIT
or STRT bit in CSR0 of the
Am79C978A controller.
BMEN is cleared by H_RESET
and is not effected by S_RESET
or by setting the STOP bit.
1
MEMEN
Memory Space Access Enable.
The Am79C978A controller will
ignore all memory accesses
when MEMEN is cleared. The
host must set MEMEN before the
first memory access to the
device.
For memory mapped I/O, the
host must program the PCI Mem-
ory Mapped I/O Base Address
register with a valid memory ad-
dress before setting MEMEN.
For accesses to the Expansion
ROM, the host must program the
PCI
Expansion
Address register at offset 30h
with a valid memory address
ROM
Base
相關(guān)PDF資料
PDF描述
AM79C978 Single-Chip 1/10 Mbps PCI Home Networking Controller
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AM79C981JC Integrated Multiport Repeater Plus⑩ (IMR+⑩)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C978KC/W 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller
AM79C978VC/W 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller
AM79C979BKC\\W 制造商:Advanced Micro Devices 功能描述:
AM79C98 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Twisted-Pair Ethernet Transceiver (TPEX)
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