170
Am79C978A
write operation has been per-
formed to BCR34. Read cycles
on the MII management inter-
face are invoked when BCR34
is read. Upon completion of the
read cycle, the 16-bit result of
the read operation is stored in
MIIMD. Write cycles on the MII
management interface are in-
voked when BCR34 is written.
The value written to MIIMD is
the value used in the data field
of the management write frame.
These bits are always read/write
accessible. MIIMD is undefined
after H_RESET and is unaffected
by S_RESET and the STOP bit.
BCR35: PCI Vendor ID Register
Note:
Bits 15-0 in this register are programmable
through the EEPROM.
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
VID
Vendor ID. The PCI Vendor ID
register is a 16-bit register that
identifies the manufacturer of the
Am79C978A controller. AMD
’
s
Vendor ID is 1022h. Note that this
Vendor ID is not the same as the
Manufacturer ID in CSR88 and
CSR89. The Vendor ID is as-
signed by the PCI Special Interest
Group.
The Vendor ID is not normally
programmable,
Am79C978A controller allows
this due to legacy operating sys-
tems that do not look at the PCI
Subsystem Vendor ID and the
Vendor ID to uniquely identify the
add-in board or subsystem that
the Am79C978A controller is
used in.
but
the
Note:
If the operating system or
the network operating system
supports PCI Subsystem Vendor
ID and Subsystem ID, use those
to identify the add-in board or
subsystem and program the VID
with the default value of 1022h
.
VID is aliased to the PCI configu-
ration space register Vendor ID
(offset 00h).
Read accessible always. VID is
read only. Write operations are
ignored. VID is set to 1022h by
H_RESET and is not affected by
S_RESET or by setting the STOP
bit.
BCR36: PCI Power Management Capabilities (PMC)
Alias Register
Note:
This register is an alias of the PMC register
located at offset 42h of the PCI Configuration Space.
Since PMC register is read only, BCR36 provides a
means of programming it through the EEPROM. The
contents of this register are copied into the PMC regis-
ter. For the definition of the bits in this register, refer to
the PMC register definition. Bits 15-0 in this register are
programmable through the EEPROM. Read accessible
always. Read only. Cleared by H_RESET and is not af-
fected by S_RESET or setting the STOP bit.
BCR37: PCI DATA Register 0 (DATA0) Alias Register
Note:
This register is an alias of the DATA register and
also of the DATA_SCALE field of the PMCSR register.
Since these two are read only, BCR37 provides a means
of programming them indirectly. The contents of this reg-
ister are copied into the corresponding fields pointed
with the DATA_SEL field set to zero. Bits 15-0 in this reg-
ister are programmable through the EEPROM.
Bit
Name
Description
15-10 RES
Reserved locations. Written as
zeros and read as undefined.
9-8
D0_SCALE
These bits correspond to the
DATA_SCALE
PMCSR (offset Register 44 of the
PCI configuration space, bits 14-
13). Refer to the description of
DATA_SCALE for the meaning of
this field.
field
of
the
Read
D0_SCALE is read only. Cleared
by H_RESET and is not affected
by S_RESET or setting the STOP
bit.
accessible
always.
7-0
DATA0
These bits correspond to the PCI
DATA register (offset Register 47
of the PCI configuration space,
bits 7-0). Refer to the description
of DATA register for the meaning
of this field.