參數(shù)資料
型號(hào)： AM79C978AVCW
廠商： ADVANCED MICRO DEVICES INC
元件分類(lèi)： 微控制器/微處理器
英文描述： Single-Chip 1/10 Mbps PCI Home Networking Controller
中文描述： 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： TQFP-144
文件頁(yè)數(shù)： 139/256頁(yè)
文件大?。?/td> 3505K
代理商： AM79C978AVCW
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Am79C978A
139
Read accessible only when either
the STOP or the SPND bit is set.
VER is read only. PARTIDU is
read only. Write operations are
ignored.
CSR92: Ring Length Conversion
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
RCON
Ring Length Conversion Regis-
ter. This register performs a ring
length conversion from an encod-
ed value as found in the initializa-
tion block to a two
’
s complement
value used for internal counting.
By writing bits 15-12 with an en-
coded ring length, a two
’
s com-
plemented value is read. The
RCON register is undefined until
written.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR100: Bus Timeout
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
MERRTO
This register contains the value of
the longest allowable bus latency
(interval between assertion of
REQ and assertion of GNT) that a
system may insert into an
Am79C978A controller master
transfer. If this value of bus laten-
cy is exceeded, then a MERR will
be indicated in CSR0, bit 11, and
an interrupt may be generated,
depending upon the setting of the
MERRM bit (CSR3, bit 11) and
the IENA bit (CSR0, bit 6).
The value in this register is inter-
preted as the unsigned number of
bus clock periods divided by two,
(i.e., the value in this register is
given in 0.1 ms increments). For
example, the value 0600h (1536
decimal) will cause a MERR to be
indicated after 153.6 ms of bus la-
tency. A value of 0 will allow an in-
finitely long bus latency, i.e., bus
timeout error will never occur.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. This regis-
ter is set to 0600h by H_RESET
or S_RESET and is unaffected by
STOP.
CSR112: Missed Frame Count
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
MFC
Missed Frame Count. Indicates
the number of missed frames.
MFC will roll over to a count of 0
from the value 65535. The MFCO
bit of CSR4 (bit 8) will be set each
time that this occurs.
Read accessible always. MFC is
read only, write operations are ig-
nored. MFC is cleared by
H_RESET, or S_RESET or by
setting the STOP bit.CSR114:
Receive Collision Count
CSR114: Receive Collision count
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
RCC
Receive Collision Count. Indi-
cates the total number of colli-
sions
encountered
receiver since the last reset of the
counter.
by
the
RCC will roll over to a count of 0
from the value 65535. The
RCVCCO bit of CSR4 (bit 5) will
be set each time that this occurs.
These bits are read accessible al-
ways. RCC is read only, write op-
erations are ignored. RCC is
cleared
by
S_RESET, or by setting the
STOP bit.
H_RESET
or
相關(guān)PDF資料
PDF描述
AM79C978 Single-Chip 1/10 Mbps PCI Home Networking Controller
AM79C981 Integrated Multiport Repeater Plus⑩ (IMR+⑩)
AM79C981JC Integrated Multiport Repeater Plus⑩ (IMR+⑩)
AM79C982 basic Integrated Multiport Repeater (bIMR)
AM79C982-4JC basic Integrated Multiport Repeater (bIMR)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C978KC/W 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller
AM79C978VC/W 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller
AM79C979BKC\\W 制造商:Advanced Micro Devices 功能描述:
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